Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al., "All-Inclusive ECC: Thorough End-to-End Protection for Reliable Computer Memory", 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA), hereinafter Kim, in view of PLONDKE et al., US 20170371739, hereinafter PLONDKE.
As per claim 1, Kim teaches A memory device, comprising:
a plurality of pins including a set of command pins; and
one or more components configured to:
receive, via the set of command pins, a set of command bits that indicates a command,
(Page 623 II-A, 2nd Para., DDR4 DRAM commands use 28 non-data pins to issue and control 4 types of signals: clock (CK), control (CTRL), command (CMD), and address (ADD)....)
EXCEPT
wherein one or more bits of the set of command bits are repurposed as parity bits relating to remaining bits of the set of command bits; and
perform a parity check using the one or more bits that are repurposed as parity bits.
PLONDKE teaches
wherein one or more bits of the set of command bits are repurposed as parity bits relating to remaining bits of the set of command bits; and ([0031] FIG. 2 shows examples where bits of instruction packet 200 (e.g., unused bits or reserved bits repurposed as parity bits) can be used for parity.)
perform a parity check using the one or more bits that are repurposed as parity bits. (Fig.1, [0030])
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified Kim to incorporate the teaching of the limitation as indicated above from PLONDKE, to make effective error checking (PLONDKE, [0005]).
As per claim 14, Kim teaches A method, comprising:
receiving, by a memory device, a mode register command that configures a parameter in a mode register of the memory device; (page 626, 1st para., Commands for DRAM initialization (mode register set and ZQ calibration))
receiving, by the memory device via a set of command pins, a set of command bits that indicates a command, (Page 623 II-A, 2nd Para., DDR4 DRAM commands use 28 non-data pins to issue and control 4 types of signals: clock (CK), control (CTRL), command (CMD), and address (ADD)....)
EXCEPT
wherein configuration of the parameter in the mode register frees a switchable parameter bit, of the set of command bits, that otherwise is used to configure the parameter, and
wherein the switchable parameter bit is used as a parity bit relating to remaining bits of the set of command bits; and
performing, by the memory device, a parity check using the switchable parameter bit that is used as the parity bit.
PLONDKE teaches
wherein configuration of the parameter in the mode register frees a switchable parameter bit, of the set of command bits, that otherwise is used to configure the parameter, and
wherein the switchable parameter bit is used as a parity bit relating to remaining bits of the set of command bits; and
([0031] FIG. 2 shows examples where bits of instruction packet 200 (e.g., unused bits or reserved bits repurposed as parity bits) can be used for parity.)
performing, by the memory device, a parity check using the switchable parameter bit that is used as the parity bit. (Fig.1, [0030])
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified Kim to incorporate the teaching of the limitation as indicated above from PLONDKE, to make effective error checking (PLONDKE, [0005]).
As per claim 20, Kim teaches A system, comprising:
a host device configured to:
transmit a set of command bits that indicates a command,
(Page 623 II-A, 2nd Para., DDR4 DRAM commands use 28 non-data pins to issue and control 4 types of signals: clock (CK), control (CTRL), command (CMD), and address (ADD)....)
EXCEPT
wherein one or more bits of the set of command bits are repurposed as parity bits relating to remaining bits of the set of command bits; and
a memory device configured to:
receive the set of command bits; and
perform a parity check using the one or more bits that are repurposed as parity bits.
PLONDKE teaches
wherein one or more bits of the set of command bits are repurposed as parity bits relating to remaining bits of the set of command bits; and
([0031] FIG. 2 shows examples where bits of instruction packet 200 (e.g., unused bits or reserved bits repurposed as parity bits) can be used for parity.)
a memory device configured to:
receive the set of command bits; and
perform a parity check using the one or more bits that are repurposed as parity bits. (Fig.1, [0030])
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified Kim to incorporate the teaching of the limitation as indicated above from PLONDKE, to make effective error checking (PLONDKE, [0005]).
As per claim 2, Kim-PLONDKE teaches The memory device applied above in claim 1, Kim further teaches wherein the set of command bits indicate the command and address information. (Page 623, 2nd para. (command and address parity / write CRC) to ease adoption and leverage prior effort.)
As per claim 3, Kim-PLONDKE teaches The memory device applied above in claim 1, PLONDKE further teaches wherein the one or more bits comprise only a single bit that is repurposed as a parity bit relating to all of the remaining bits.
([0031] FIG. 2 shows examples where bits of instruction packet 200 (e.g., unused bits or reserved bits repurposed as parity bits) can be used for parity.)
As per claim 15, Kim-PLONDKE teaches The method applied above in claim 14, Kim further teaches wherein the switchable parameter bit is used as a parity bit relating to all of the remaining bits.
([0031] FIG. 2 shows examples where bits of instruction packet 200 (e.g., unused bits or reserved bits repurposed as parity bits) can be used for parity.)
As per claim 4, Kim-PLONDKE teaches The memory device applied above in claim 1, PLONDKE further teaches wherein the one or more bits comprise a first bit that is repurposed as a first parity bit relating to a first portion of the remaining bits, and a second bit that is repurposed as a second parity bit relating to a second portion of the remaining bits.
([0034] the right or least significant bit position of the 2-bit field may be repurposed for use in parity)
As per claim 16, Kim-PLONDKE teaches The method applied above in claim 14, Kim further teaches wherein the switchable parameter bit is a first switchable parameter bit, and the set of command bits further comprises a second switchable parameter bit that is freed through configuration in the mode register, and
wherein the first switchable parameter bit is used as a first parity bit relating to a first portion of the remaining bits, and the second switchable parameter bit is used as a second parity bit relating to a second portion of the remaining bits.
([0034] the right or least significant bit position of the 2-bit field may be repurposed for use in parity)
As per claim 5, Kim-PLONDKE teaches The memory device applied above in claim 1, Kim further teaches wherein a definition of the command indicates two reserved for future use (RFU) bits for the command, and
wherein the one or more bits, that are repurposed as parity bits, comprise the two RFU bits.
(Page 627, Fig.5(e) Reserved; Page 629, TABLE II, a reserved-for-future-use command)
As per claim 17, Kim-PLONDKE teaches The method applied above in claim 14, Kim further teaches wherein the set of command bits further comprises a reserved for future use (RFU) bit, and
wherein the switchable parameter bit is used as a first parity bit relating to a first portion of the remaining bits, and the RFU bit is used as a second parity bit relating to a second portion of the remaining bits.
(Page 627, Fig.5(e) Reserved; Page 629, TABLE II, a reserved-for-future-use command)
As per claim 21, Kim-PLONDKE teaches The system applied above in claim 20, Kim further teaches wherein a definition of the command indicates two reserved for future use (RFU) bits for the command, and
wherein the one or more bits, that are repurposed as parity bits, comprise the two RFU bits.
(Page 627, Fig.5(e) Reserved; Page 629, TABLE II, a reserved-for-future-use command)
As per claim 6, Kim-PLONDKE teaches The memory device applied above in claim 1, Kim further teaches wherein a definition of the command indicates one reserved for future use (RFU) bit and one switchable parameter bit for the command, and
wherein the one or more bits, that are repurposed as parity bits, comprise the one RFU bit and the one switchable parameter bit.
(Page 627, Fig.5(e) Reserved; Page 629, TABLE II, a reserved-for-future-use command)
As per claim 22, Kim-PLONDKE teaches The system applied above in claim 20, Kim further teaches wherein a definition of the command indicates one reserved for future use (RFU) bit and one switchable parameter bit for the command, and
wherein the one or more bits, that are repurposed as parity bits, comprise the one RFU bit and the one switchable parameter bit.
(Page 627, Fig.5(e) Reserved; Page 629, TABLE II, a reserved-for-future-use command)
As per claim 7, Kim-PLONDKE teaches The memory device applied above in claim 1, Kim further teaches wherein a definition of the command indicates zero reserved for future use (RFU) bits and two switchable parameter bits for the command, and
wherein the one or more bits, that are repurposed as parity bits, comprise the two switchable parameter bits.
(Page 627, Fig.5(e) Reserved; Page 629, TABLE II, a reserved-for-future-use command)
As per claim 23, Kim-PLONDKE teaches The system applied above in claim 20, Kim further teaches wherein a definition of the command indicates zero reserved for future use (RFU) bits and two switchable parameter bits for the command, and
wherein the one or more bits, that are repurposed as parity bits, comprise the two switchable parameter bits.
(Page 627, Fig.5(e) Reserved; Page 629, TABLE II, a reserved-for-future-use command)
As per claim 8, Kim-PLONDKE teaches The memory device applied above in claim 1, Kim further teaches wherein the one or more components are further configured to receive, via the set of command pins, an additional set of command bits that indicate a different command,
wherein a definition of the different command indicates zero reserved for future use (RFU) bits and zero switchable parameter bits for the different command, and
wherein the one or more bits are repurposed as parity bits relating to the remaining bits of the set of command bits, and relating to the additional set of command bits.
(Page 627, Fig. 5(g), 5(h))
As per claim 9, Kim-PLONDKE teaches The memory device applied above in claim 1, Kim further teaches wherein a definition of the command indicates a switchable parameter bit for the command, and
wherein a parameter indicated by the switchable parameter bit is configured in a mode register to free the switchable parameter bit for use as a parity bit.
(page 626, 1st para., Commands for DRAM initialization (mode register set and ZQ calibration); Page 627, Fig. 5(h); Page 628, D. Extended CA Parity (eCAP))
As per claim 24, Kim-PLONDKE teaches The system applied above in claim 20, Kim further teaches wherein a definition of the command indicates a switchable parameter bit for the command, and
wherein a parameter indicated by the switchable parameter bit is configured in a mode register to free the switchable parameter bit for use as a parity bit.
(page 626, 1st para., Commands for DRAM initialization (mode register set and ZQ calibration); Page 627, Fig. 5(h); Page 628, D. Extended CA Parity (eCAP))
As per claim 10, Kim-PLONDKE teaches The memory device applied above in claim 9, Kim further teaches wherein the parameter is a clock synchronization parameter, an efficiency mode parameter, or an auto precharge parameter.
(Page 627-628, C. Command State and Timing Checker, TABLE I: DRAM commands with their allowed bank state and timing constraints.
D. Extended CA Parity (eCAP), 1st para. the memory controller and memory maintain synchronized write toggle (WRT) bits that flip upon sending/receiving a WR command)
As per claim 18, Kim-PLONDKE teaches The method applied above in claim 14, Kim further teaches wherein the parameter is a clock synchronization parameter, an efficiency mode parameter, or an auto precharge parameter.
(Page 627-628, C. Command State and Timing Checker, TABLE I: DRAM commands with their allowed bank state and timing constraints.
D. Extended CA Parity (eCAP), 1st para. the memory controller and memory maintain synchronized write toggle (WRT) bits that flip upon sending/receiving a WR command)
As per claim 25, Kim-PLONDKE teaches The system applied above in claim 24, Kim further teaches wherein the parameter is a clock synchronization parameter, an efficiency mode parameter, or an auto precharge parameter.
(Page 627-628, C. Command State and Timing Checker, TABLE I: DRAM commands with their allowed bank state and timing constraints.
D. Extended CA Parity (eCAP), 1st para. the memory controller and memory maintain synchronized write toggle (WRT) bits that flip upon sending/receiving a WR command)
As per claim 11, Kim-PLONDKE teaches The memory device applied above in claim 1, Kim further teaches wherein a definition of the command indicates multiple column address bits that indicate address information for the command, and
wherein the one or more bits, that are repurposed as parity bits, comprise one or more of the multiple column address bits.
(Fig.5(f) An overview of Extended Write CRC (eWCRC))
As per claim 12, Kim-PLONDKE teaches The memory device applied above in claim 1, Kim further teaches wherein the one or more components, to receive the set of command bits, are configured to receive the set of command bits by double data rate (DDR) signaling.
(page 628, Chap IV-Section, C. Command State and Timing Checker, 1st para. "Table I shows the bank state and timing constraints for DDR4 DRAM"; D. Extended CA Parity (eCAP), 1st para. we extend the CA parity of DDR4 to cover missing WR commands (Figure 5h).)
As per claim 19, Kim-PLONDKE teaches The method applied above in claim 14, Kim further teaches wherein the set of command bits are received by double data rate (DDR) signaling.
(page 628, Chap IV-Section, C. Command State and Timing Checker, 1st para. "Table I shows the bank state and timing constraints for DDR4 DRAM"; D. Extended CA Parity (eCAP), 1st para. we extend the CA parity of DDR4 to cover missing WR commands (Figure 5h).)
As per claim 13, Kim-PLONDKE teaches The memory device applied above in claim 1, Kim further teaches wherein the memory device comprises dynamic random-access memory (DRAM). (Fig. 1, DRAM)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Boehm et al., US 20210318928, TARGETED COMMAND/ADDRESS PARITY LOW LIFT
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/RONG TANG/Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111
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