Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
directed to non-statutory subject matter as they fail to remedy the independent claims.
35 U.S.C. 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103(a) as being unpatentable over Tekumalla (US Pub. No. 2012/0331362) in view of Mukherjee et al. (US Pub. No. 2013/0305107).
With respect to claim 1, the Tekumalla reference teaches a scan chain comprising a first plural number (N) of states, each of the stages configured to store a bit ([0033] - state when data is being shifted into and out of the scan chains 108 and therefore the scan capture clock signal remains inactive).
The Tekumalla reference does not teach and a second plural number(S) of multiplexers operatively coupled to the scan chain; wherein the S is determined based on the N.
The Mukherjee et al. reference teaches and a second plural number(S) of multiplexers operatively coupled to the scan chain ([0169] - the outputs of the overdrive register could be coupled to the inputs of the first compactor through a feedback network comprises multiplexers. The overdrive register, scan chains, and multiplexer could then be controlled by a control circuit (for example, a finite state machine) to operate the first compactor as a second compactor every v scan shift cycles); wherein the S is determined based on the N ([0169] - the outputs of the overdrive register could be coupled to the inputs of the first compactor through a feedback network comprises multiplexers. The overdrive register, scan chains, and multiplexer could then be controlled by a control circuit (for example, a finite state machine) to operate the first compactor as a second compactor every v scan shift cycles).
Thus, it would have been obvious to one of ordinary skill in the art at the time of the invention was made to have combined the references Tekumalla and Mukherjee et al. to incorporate and a second plural number(S) of multiplexers operatively coupled to the scan chain; wherein the S is determined based on the N into the claimed invention.
The motivation for wherein the S is determined based on the N to reduce states ([0004 – Mukherjee et al. ).
With respect to claims 2, 13 and 20, all of the limitations of claim 1, 12 and 19 have been addressed.
The Tekumalla reference does not teach wherein the S is equal to N/M, where the M represents a diagnostic resolution.
The Mukherjee et al. reference teaches wherein the S is equal to N/M, where the M represents a diagnostic resolution ([0169] - the outputs of the overdrive register could be coupled to the inputs of the first compactor through a feedback network comprises multiplexers. The overdrive register, scan chains, and multiplexer could then be controlled by a control circuit (for example, a finite state machine) to operate the first compactor as a second compactor every v scan shift cycles) and ([0163] Table 9 below shows average diagnostic resolutions for some circuit designs used to produce experimental results described elsewhere in this application. In Table 9, the second column lists the average diagnostic resolution without compression, while the next column lists the same resolution using an exemplary embodiment of the X-Press compactor).
Thus, it would have been obvious to one of ordinary skill in the art at the time of the invention was made to have combined the references Tekumalla and Mukherjee et al. to incorporate wherein the S is equal to N/M, where the M represents a diagnostic resolution into the claimed invention.
The motivation for wherein the S is equal to N/M, where the M represents a diagnostic resolution to reduce states ([0004 – Mukherjee et al. ).
With respect to claim 3, the Tekumalla reference teaches wherein the multiplexers are each configured to receive a respective one of S control signals to selectively bypass a corresponding subset of the stages ([0041] - bypass and SE are at logic low levels, and the output of OR gate 315 provides the appropriate number of capture pulses).
With respect to claims 4, the Tekumalla reference teaches wherein a number of the subset of stages bypassed is equal to M ([0041] - bypass and SE are at logic low levels, and the output of OR gate 315 provides the appropriate number of capture pulses).
With respect to claim 5, the Tekumalla reference teaches wherein a number of combinations of the S control signals is equal to S+1 ([0338] - clock selection circuit 204 further comprises an OR gate 502 having a first input adapted to receive the shift enable signal SE and a second input adapted to receive an additional signal denoted bypass. The output of the OR gate 502 drives the select line of the multiplexer 500).
With respect to claim 6, the Tekumalla reference teaches wherein a first one of the multiplexers has: a first input connected to an output of a second one of the multiplexers ([0029] - first input coupled to an output of the finite state machine 300 and a second input coupled to the output of a corresponding one of the capture clock pulse circuits 302, 303 and 304, and an output OR gate 315. The output OR gate 315 has inputs coupled to respective outputs of the first, second and third AND gates 312, 313 and 314, and an output providing the particular one of the capture clock pulse signals based on the current state of the finite state machine); a second input connected to an output of a corresponding subset of stages ([0029] - first input coupled to an output of the finite state machine 300 and a second input coupled to the output of a corresponding one of the capture clock pulse circuits 302, 303 and 304, and an output OR gate 315. The output OR gate 315 has inputs coupled to respective outputs of the first, second and third AND gates 312, 313 and 314, and an output providing the particular one of the capture clock pulse signals based on the current state of the finite state machine) ; and an output connected to a first input of a third one of the multiplexers ([0029] - output providing the particular one of the capture clock pulse signals based on the current state of the finite state machine).
With respect to claim 7, the Tekumalla reference teaches wherein the second multiplexer, the first multiplexer, and the third multiplexer are connected in such an order along a direction from a scan input of the scan chain to a scan output of the scan chain ([0029] - first input coupled to an output of the finite state machine 300 and a second input coupled to the output of a corresponding one of the capture clock pulse circuits 302, 303 and 304, and an output OR gate 315. The output OR gate 315 has inputs coupled to respective outputs of the first, second and third AND gates 312, 313 and 314, and an output providing the particular one of the capture clock pulse signals based on the current state of the finite state machine).
With respect to claim 8, the Tekumalla reference teaches wherein the first multiplexer is configured to selectively couple the output of the corresponding subset of stages to the first input of the third multiplexer or couple the output of the second multiplexer to the first input of the third multiplexer ([0029] - first input coupled to an output of the finite state machine 300 and a second input coupled to the output of a corresponding one of the capture clock pulse circuits 302, 303 and 304, and an output OR gate 315. The output OR gate 315 has inputs coupled to respective outputs of the first, second and third AND gates 312, 313 and 314, and an output providing the particular one of the capture clock pulse signals based on the current state of the finite state machine).
With respect to claim 9, the Tekumalla reference teaches wherein the corresponding subset of stages are thus bypassed ([0041] - bypass and SE are at logic low levels, and the output of OR gate 315 provides the appropriate number of capture pulses)..
With respect to claims 10 and 17, the Tekumalla reference teaches wherein a defect location at any subset of the stages is determined based at least on comparing a first data pattern and a second data pattern, wherein the first data pattern and the second data pattern are unloaded by the scan chain based on a first combination of the control signals and a second combination of the control signals, respectively ([0026] - variable number of capture pulses facilitates testing of the functional logic 104A and 104B that is not covered by the MBIST testing implemented using MBIST controller 106. For example, such an arrangement allows the functional logic to be tested using at-speed clocks, such that the test environment closely tracks the functional operating environment. The scan test controller 110 takes into account variations in capture pulse requirements for particular test patterns and generates an appropriate number of at-speed capture pulses).
With respect to claim 11 and 18, the Tekumalla reference teaches wherein the first combination of the control signals and the second combination of the control signals are different from each other with only one bit ([0026] - The scan test controller 110 takes into account variations in capture pulse requirements for particular test patterns and generates an appropriate number of at-speed capture pulses).
With respect to claim 12, the Tekumalla reference teaches a scan chain comprising a cell structure, wherein the cell structure comprises a first plural number (N) of stages, and each of the stages is configured to store a bit ([0033] - state when data is being shifted into and out of the scan chains 108 and therefore the scan capture clock signal remains inactive).
The Tekumalla reference does not teach a second plural number(S) of multiplexers operatively coupled to the N stages and configured to selectively bypass a corresponding one of subsets of the stages, wherein the S is a factor of the N.
The Mukherjee et al. reference teaches a second plural number(S) of multiplexers operatively coupled to the N stages ([0169] - the outputs of the overdrive register could be coupled to the inputs of the first compactor through a feedback network comprises multiplexers. The overdrive register, scan chains, and multiplexer could then be controlled by a control circuit (for example, a finite state machine) to operate the first compactor as a second compactor every v scan shift cycles); and configured to selectively bypass a corresponding one of subsets of the stages, wherein the S is a factor of the N ([0169] - the outputs of the overdrive register could be coupled to the inputs of the first compactor through a feedback network comprises multiplexers. The overdrive register, scan chains, and multiplexer could then be controlled by a control circuit (for example, a finite state machine) to operate the first compactor as a second compactor every v scan shift cycles) and ([0041] - bypass and SE are at logic low levels, and the output of OR gate 315 provides the appropriate number of capture pulses.
Thus, it would have been obvious to one of ordinary skill in the art at the time of the invention was made to have combined the references Tekumalla and Mukherjee et al. to incorporate a second plural number(S) of multiplexers operatively coupled to the N stages and configured to selectively bypass a corresponding one of subsets of the stages, wherein the S is a factor of the N into the claimed invention.
The motivation for wherein the S is determined based on the N to reduce states ([0004 – Mukherjee et al. ).
With respect to claim 14, the Tekumalla reference teaches wherein a first one, a second one, and a third one of the multiplexers are connected in such an order along a direction from a scan input of the scan chain to a scan output of the scan chain ([0029] - first input coupled to an output of the finite state machine 300 and a second input coupled to the output of a corresponding one of the capture clock pulse circuits 302, 303 and 304, and an output OR gate 315. The output OR gate 315 has inputs coupled to respective outputs of the first, second and third AND gates 312, 313 and 314, and an output providing the particular one of the capture clock pulse signals based on the current state of the finite state machine).
With respect to claim 15, the Tekumalla reference teaches wherein each of the multiplexers has: a first input ([0029] - first, second and third AND gates 312, 313 and 314, each having a first input coupled to an output of the finite state machine 300) ; a second input ([0029] - first, second and third AND gates 312, 313 and 314, each having a first input coupled to an output of the finite state machine 300 and a second input coupled to the output of a corresponding one of the capture clock pulse circuits 302, 303 and 304, and an output OR gate 315); and an output ([0029] - first, second and third AND gates 312, 313 and 314, each having a first input coupled to an output of the finite state machine 300 and a second input coupled to the output of a corresponding one of the capture clock pulse circuits 302, 303 and 304, and an output OR gate 315); wherein the first input of the first multiplexer is coupled to the scan input ([0029] - first, second and third AND gates 312, 313 and 314, each having a first input coupled to an output of the finite state machine 300 and a second input coupled to the output of a corresponding one of the capture clock pulse circuits 302, 303 and 304, and an output OR gate 315); the second input of the first multiplexer is connected to an output of a first subset of the stages, and the output of the first multiplexer is connected to the first input of the second multiplexer ([0029] - first input coupled to an output of the finite state machine 300); wherein the second input of the second multiplexer is connected to an output of a second subset of the stages, and the output of the second multiplexer is connected to the first input of the third multiplexer ([0029] - The output OR gate 315 has inputs coupled to respective outputs of the first, second and third AND gates 312, 313 and 314, and an output providing the particular one of the capture clock pulse signals based on the current state of the finite state machine) ; and wherein the second input of the third multiplexer is connected to an output of a third subset of the stages, and the output of the third multiplexer is coupled to the scan output ([0029] - The output OR gate 315 has inputs coupled to respective outputs of the first, second and third AND gates 312, 313 and 314, and an output providing the particular one of the capture clock pulse signals based on the current state of the finite state machine).
With respect to claim 16, the Tekumalla reference teaches wherein a number of combinations of the S control signals is equal to S+1 ([0041] - bypass and SE are at logic low levels, and the output of OR gate 315 provides the appropriate number of capture pulses).
With respect to claim 18, the Tekumalla reference teaches wherein a number of combinations of the S control signals is equal to S+1 ([0041] - bypass and SE are at logic low levels, and the output of OR gate 315 provides the appropriate number of capture pulses).
With respect to claim 19, the Tekumalla reference teaches a scan chain comprising a cell structure, wherein the cell structure comprises a first plural number (N) of stages, and each of the stages is configured to store a bit ([0033] - state when data is being shifted into and out of the scan chains 108 and therefore the scan capture clock signal remains inactive).
The Tekumalla reference does not teach a second plural number(S) of multiplexers operatively coupled to the scan chain, wherein the S is determined based on the N; wherein the multiplexers are each configured to receive a respective one of S control signals to selectively bypass a corresponding subset of the stages..
The Mukherjee et al. reference teaches a second plural number(S) of multiplexers operatively coupled to the scan chain, wherein the S is determined based on the N ([0169] - the outputs of the overdrive register could be coupled to the inputs of the first compactor through a feedback network comprises multiplexers. The overdrive register, scan chains, and multiplexer could then be controlled by a control circuit (for example, a finite state machine) to operate the first compactor as a second compactor every v scan shift cycles); wherein the multiplexers are each configured to receive a respective one of S control signals to selectively bypass a corresponding subset of the stages ([0169] - the outputs of the overdrive register could be coupled to the inputs of the first compactor through a feedback network comprises multiplexers. The overdrive register, scan chains, and multiplexer could then be controlled by a control circuit (for example, a finite state machine) to operate the first compactor as a second compactor every v scan shift cycles) and ([0041] - bypass and SE are at logic low levels, and the output of OR gate 315 provides the appropriate number of capture pulses).
Thus, it would have been obvious to one of ordinary skill in the art at the time of the invention was made to have combined the references Tekumalla and Mukherjee et al. to incorporate a second plural number(S) of multiplexers operatively coupled to the N stages and configured to selectively bypass a corresponding one of subsets of the stages, wherein the S is a factor of the N into the claimed invention.
The motivation for wherein the S is determined based on the N to reduce states ([0004 – Mukherjee et al.).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Enam Ahmed whose telephone number is 571-270-1729. The examiner can normally be reached on Mon-Fri from 8:30 A.M. to 5:30 P.M. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Albert Decady, can be reached on 571-272-3819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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EA
5/25/26
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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