DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priorities
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. JP2018-085668, filed on 04/26/2018.
Information Disclosure Statement
The information disclosure statements filed 06/30/2025 has been acknowledged and considered by the examiner. An initialed copy of the PTO-1449 is included in this correspondence.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ohara et al. (US Pub. 2016/0012774 A1).
Regarding claim 1; Ohara teaches a display device (a display device 1, Fig.2) comprising:
[AltContent: arrow][AltContent: textbox (First circuit 47)][AltContent: rect][AltContent: rect][AltContent: arrow][AltContent: textbox (Second circuit)][AltContent: arrow][AltContent: textbox (Third circuit)]
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(Fig.28 of Ohara reproduced)
a source driver (a source driver 200, Fig.2);
a first circuit (a first circuit 47, Fig.28 reproduced above) electrically connected to the source driver (Fig.2, the first circuit 47 is connected to the source driver 200 via a data line DL);
a second circuit (a second circuit as annotated in Fig.28 above) electrically connected to the first circuit (see Fig.28 above); and
a third circuit (a third circuit as annotated in Fig.28 reproduced above) electrically connected to the first circuit (see Fig.28 above),
wherein the first circuit (the first circuit 47) comprises a first transistor (a transistor T2), a second transistor (a transistor T7), and a capacitor (a capacitor Cst),
wherein the second circuit (the second circuit, Fig.28) comprises a first display element (an OLED (R)),
wherein the third circuit (the third circuit, Fig.28) comprises a second display element (an OLED (G)),
wherein one of a source and a drain of the first transistor (the transistor T2, Fig.28) is electrically connected to the source driver (Fig.28, one of a source or drain terminal of the transistor T2 is connected to the source driver 200 via the data line DL),
wherein the other of the source and the drain of the first transistor is electrically connected to a first electrode of the capacitor (Fig.28, the other of the source and drain terminal of the transistor T2 is connected to one electrode of the capacitor Cst),
wherein one of a source and a drain of the second transistor is electrically connected to a second electrode of the capacitor (Fig.28, one of a source or drain terminal of the transistor T7 is connected to another electrode of the capacitor Cst),
wherein the first circuit (the first circuit 47, Fig.28) is configured to be supplied first data from the source driver (Fig.28, the first circuit 47 receives data voltage from the source driver 200 via the data line DL) and add second data to the first data (Fig.28, the first circuit 47 also receives a reference voltage from a reference voltage line REF. A combination of data voltage and the reference voltage is applied to a gate terminal of a driving transistor T1),
wherein each of the first display element (the OLED (R)) and the second display element (the OLED (G)) is configured to display based on data obtained by adding the second data to the first data (Fig.28, para. [0215-0219], the capacitor Cst is charged by a voltage difference between the reference voltage VREF and the data voltage Vdata),
wherein the first data comprises image data (Fig.28, para. [0219], the data voltage Vdata is supplied from the data line DL), and wherein the second data comprises correction data (Fig.28, para. [0219], the reference voltage VREF is supplied from the reference voltage line REF).
Regarding claim 2; Ohara teaches the display device of claim 1 as discussed above. Ohara further teaches each of the first display element and the second display element is a light-emitting element (see Fig.28; OLED (R), OLED (G), and OLED (B)).
Regarding claim 3; Ohara teaches the display device of claim 1 as discussed above. Ohara further teaches at least one of the first transistor and the second transistor has a channel formation region comprising a metal oxide, wherein the metal oxide comprises In, Zn, and an element M, and wherein the element M is selected from the group consisting of Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, and Hf (para. [0077 and 0079], the transistors are thin-film transistors whose channel layers are formed of an oxide semiconductor having main components including: indium (In), gallium (Ga), zinc (Zn), and oxygen (O)).
Regarding claim 4; Ohara teaches the display device of claim 1 as discussed above. Ohara further teaches at least one of the first transistor and the second transistor has a channel formation region comprising a metal oxide, and wherein the metal oxide comprises In (para. [0077 and 0079], the transistors are thin-film transistors whose channel layers are formed of an oxide semiconductor having main components including: indium (In), gallium (Ga), zinc (Zn), and oxygen (O)).
Regarding claim 5; Ohara teaches a display device comprising:
a source driver (a source driver 200, Fig.2);
a first circuit (a first circuit 47 as shown in Fig.28 reproduced above) electrically connected to the source driver (Figs. 2 and 28);
a second circuit (a second circuit as shown in Fig.28 reproduced above) electrically connected to the first circuit (Fig.28); and
a third circuit (a third circuit as shown in Fig.28 reproduced above) electrically connected to the first circuit (Fig.28),
wherein the first circuit (the first circuit47) comprises a first transistor (a transistor T2), a second transistor (a transistor T7), and a capacitor (a capacitor Cst),
wherein the second circuit (the second circuit) comprises a first display element (an OLED (R)) and a third transistor (a transistor T3) electrically connected to the first display element (Fig.28),
wherein the third circuit (the third circuit) comprises a second display element (an OLED (G)) and a fourth transistor (a transistor T4) electrically connected to the second display element (Fig.28),
wherein one of a source and a drain of the first transistor is electrically connected to the source driver (Fig.28, one of a source and a drain terminal of the transistor T2 is connected to the source driver 200 via the data line DL),
wherein the other of the source and the drain of the first transistor is electrically connected to a first electrode of the capacitor (Fig.28, the other of the source and drain terminals of the transistor T2 is connected to one electrode of the capacitor Cst),
wherein one of a source and a drain of the second transistor is electrically connected to a second electrode of the capacitor (Fig.28, one of a source and a drain terminals of the transistor T7 is connected to another terminal of the capacitor Cst),
wherein the third transistor (the transistor T3) and the fourth transistor (the transistor T4) are electrically connected to the capacitor (Fig.28, the transistors T3 and T4 are connected to the capacitor Cst),
wherein the first circuit (the first circuit 47, Fig.28) is configured to be supplied first data from the source driver (Fig.28, the first circuit 47 receives data voltage from the source driver 200 via the data line DL) and add second data to the first data (Fig.28, the first circuit 47 also receives a reference voltage from a reference voltage line REF. A combination of data voltage and the reference voltage is applied to a gate terminal of a driving transistor T1),
wherein each of the first display element (the OLED (R)) and the second display element (the OLED (G)) is configured to display based on data obtained by adding the second data to the first data (Fig.28, para. [0215-0219], the capacitor Cst is charged by a voltage difference between the reference voltage VREF and the data voltage Vdata),
wherein the first data comprises image data (Fig.28, para. [0219], the data voltage Vdata is supplied from the data line DL), and wherein the second data comprises correction data (Fig.28, para. [0219], the reference voltage VREF is supplied from the reference voltage line REF).
Regarding claim 6; Ohara teaches the display device of claim 5 as discussed above. Ohara further teaches each of the first display element and the second display element is a light-emitting element (see Fig.28; OLED (R), OLED (G), and OLED (B)).
Regarding claim 7; Ohara teaches the display device of claim 5 as discussed above. Ohara further teaches at least one of the first transistor and the second transistor has a channel formation region comprising a metal oxide, wherein the metal oxide comprises In, Zn, and an element M, and wherein the element M is selected from the group consisting of Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, and Hf (para. [0077 and 0079], the transistors are thin-film transistors whose channel layers are formed of an oxide semiconductor having main components including: indium (In), gallium (Ga), zinc (Zn), and oxygen (O)).
Regarding claim 8; Ohara teaches the display device of claim 5 as discussed above. Ohara further teaches at least one of the first transistor and the second transistor has a channel formation region comprising a metal oxide, and wherein the metal oxide comprises In (para. [0077 and 0079], the transistors are thin-film transistors whose channel layers are formed of an oxide semiconductor having main components including: indium (In), gallium (Ga), zinc (Zn), and oxygen (O)).
Regarding claim 9; Ohara teaches the display device of claim 5 as discussed above. Ohara further teaches at least one of the third transistor and the fourth transistor has a channel formation region comprising a metal oxide, wherein the metal oxide comprises In, Zn, and an element M, and wherein the element M is selected from the group consisting of Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, and Hf (para. [0077 and 0079], the transistors are thin-film transistors whose channel layers are formed of an oxide semiconductor having main components including: indium (In), gallium (Ga), zinc (Zn), and oxygen (O)).
Regarding claim 10; Ohara teaches the display device of claim 5 as discussed above. Ohara further teaches at least one of the third transistor and the fourth transistor has a channel formation region comprising a metal oxide, and wherein the metal oxide comprises In (para. [0077 and 0079], the transistors are thin-film transistors whose channel layers are formed of an oxide semiconductor having main components including: indium (In), gallium (Ga), zinc (Zn), and oxygen (O)).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Han et al. (US Pub. 2014/0139510 A1) discloses a method of driving a pixel circuit in a data charging period in which a difference voltage between a data voltage and a reference voltage is charged into a capacitor. Data current flowing in a light emitting element OLED during a light emitting period is determined based on the difference between the data voltage and the reference voltage independently from a change in threshold voltage/mobility of the driving transistor. Therefore, the display device may drive each pixel P with the pixel data DATA in which the detection data Dsen corresponding to the threshold voltage/mobility of the driving transistor DT of the pixel P is reflected, thereby compensating for a threshold voltage deviation of the driving transistor DT of the pixel P at intervals or in real time.
Yoon et al. (US Pub. 2013/0162617 A1) discloses a method of sensing characteristics of a driving TFT by summing a data voltage compensated for detected threshold voltage Vth and a reference voltage, and adjusting input based on result of the sensing.
Inquiries
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NGUYEN H TRUONG whose telephone number is (571)270-1630. The examiner can normally be reached M-F: 10-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached at 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NGUYEN H TRUONG/Examiner, Art Unit 2623
/CHANH D NGUYEN/Supervisory Patent Examiner, Art Unit 2623