DETAILED ACTION
The action is responsive to the following communications: the Application filed April 07, 2025. This application is a CON of 18/148,763.
Claims 1-20 are pending. Claims 1, 11 and 20 are independent.
Notice of Pre-AIA or AIA Status
The present application is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention, OPERATING METHOD FOR A MEMORY, A MEMORY, AND A MEMORY SYSTEM, is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Drawings
The drawings are objected to because:
Figures 1, 2a and 2b should be designated by a legend such as –Prior Art—because only that which is old is illustrated. See MPEP 608.02(g).
Applicant is reminded of helpful scenario 7, described in MPEP 2004, and encouraged to carefully review instant application’s Specification and Figures to make sure care is taken to see that prior art or other information cited in the Specification and Figures or in an information disclosure statement is properly described and that the information is not incorrectly or incompletely characterized. MPEP 2004, Scenario 7; see also MPEP 2010.
Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of US Patent No. 12,293,084. Although the claims at issue are not identical, they are not patentably distinct from each other.
Instant Application
US Patent 12,293,084
Comment
Claim 1. A method for operating a memory device, comprising:
performing a program operation of target memory cells, applying a first initial program voltage to a first word line coupled with the target memory cells;
after the program operation of the target memory cells, performing a first sensing operation and a second sensing operation of bit lines coupled with the target memory cells;
obtaining a first sensing result of the first sensing operation and a second sensing result of the second sensing operation; and
obtaining a second initial program voltage based at least on the first sensing result and the second sensing result.
Claim 1. An operating method for a memory, the memory including at least a plurality of word lines and a plurality of strings, the plurality of word lines including a target word
line, and each of the word lines being coupled to the plurality of strings, each of the strings including a plurality of memory cells, and the operating method comprising at least:
applying a first start program voltage to the target word line;
increasing a preset step voltage based on the first start program voltage to perform a first programming operation
on a plurality of target memory cells in a target string coupled to the target word line;
during performing the first programming operation and
upon each time the preset step voltage is added to the target word line, performing a first verification on the plurality of target memory cells with a first verify voltage to obtain a first verification result;
when the first verification result indicates that the plurality
of target memory cells pass the first verification for a first time, performing a second verification on the
plurality of target memory cells with a second verify voltage, wherein the first verify voltage is lower than
the second verify voltage, and a difference between the first verify voltage and the second verify voltage is lower than the preset step voltage;
obtaining a second verification result of the second verification;
determining a second start program voltage based at least on the second verification result, wherein determining the second start program voltage further includes:
determining a program voltage offset based on the second verification result, wherein when the second
verification result indicates that the plurality of target memory cells pass the second verification, the program
voltage offset is configured as a first offset value, and when the second verification result indicates
that the plurality of target memory cells fail the second verification, the program voltage offset is configured as a second offset value; and
summing of the first start program voltage, a total increase of the preset step voltage, and the program
voltage offset to define the second start program voltage, wherein the first offset value and the second
offset value are negative values, and an absolute value of the second offset value is smaller than an absolute value of the first offset value; and
applying the second start program voltage to other memory cells other than the plurality of target memory
cells to perform a second programming operation on
the other memory cells.
Note footnote1
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 11-13 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US 2012/0069674).
Regarding independent claims 1, 11 and 20, the claimed limitation(s) of first and second verification (reading / sensing) operations (such as a coarse-fine verification operation) is a well-known technology for a type of memory (e.g., flash memory) for its purpose.
For support, of the above asserted facts, see for example, Lee discloses A method for operating a memory device (see e.g., FIG. 1), comprising:
performing a program operation of target memory cells, applying a first initial program voltage to a first word line coupled with the target memory cells (FIG. 1: 1st Program pulse, and FIG. 9: S20);
after the program operation of the target memory cells, performing a first sensing operation (FIG. 1: 1st C) and a second sensing operation (1st F) of bit lines coupled with the target memory cells (FIG. 9: S50, coarse sensing for claimed 1st sensing, and fine sensing for claimed 2nd sensing);
obtaining a first sensing result of the first sensing operation and a second sensing result of the second sensing operation (FIG. 9: S70); and
obtaining a second initial program voltage based at least on the first sensing result and the second sensing result (FIG. 9: S80) (see e.g., FIGS. 1 and 9 and accompanying disclosure).
Regarding claims 2 and 12, which depends from claims 1 and 11, respectively, Lee discloses applying the second initial program voltage to a second word line different from the first word line (see e.g., para. 0060: … applied to a selected word line … performs another … verify operation on the programmed memory cell; and para. 0061:… through word lines WL<0> through WL<31> …, i.e., different a selected word line2).
Regarding claims 3 and 13, which depends from claims 1 and 11, respectively, Lee discloses during performing the program operation of the target memory cells further comprises: applying a first incremental program voltage to the first word line; and applying a Nth incremental program voltage to the first word line, N is a positive integer greater than or equal to 1, wherein the first incremental program voltage increases a preset step voltage based on the first initial program voltage, and the Nth incremental program voltage increases N the preset step voltage based on the first initial program voltage (see e.g., FIGS. 1 and 6-9, and accompanying disclosure).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-5 and 14-15 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Lee (US 2012/0069674) in view of e.g., Kim (US 2011/0292724).
Regarding claims 4 and 14, Lee teaches the limitations of claims 3 and 13, respectively.
Lee further teaches performing the first sensing operation and the second sensing operation of the bit lines comprises: applying a first verify voltage to the first word line to perform a first verification on the target memory cells; and applying a second verify voltage to the first word line to performing a second verification on the target memory cells (see e.g., FIGS. 1 and 6-9, and accompanying disclosure).
Lee is silent with respect to the first verify voltage is lower than the second verify voltage.
However, increasing the voltage during the verification phase is a well-known technology for a type of memory (e.g., flash memory) for its purpose.
For support, of the above asserted facts, see for example, Kim, e.g., FIG. 11 and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Kim to the teaching of Lee such that a memory, as taught by Lee, utilizes a step voltage, as taught by Kim, for the purpose of performing multi-verification operations and further, these conventional technology are well established in the art of the memory devices.
Regarding claims 5 and 15, Lee and Kim, as combined, teach the limitations of claims 4 and 14, respectively.
Kim further teaches a difference between the first verify voltage and the second verify voltage is lower than the preset step voltage (see e.g., FIG. 5, the step voltage is significantly larger than that voltage difference).
It would have been obvious to one of ordinary skill in the art before the effective filing date to further modify the invention of Kim for the same purpose of performing multi-verification operations effectively.
Claims 9 and 19 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Lee (US 2022/0069674).
Regarding claims 9 and 19, Lee teaches the limitations of claims 1 and 11, respectively.
Lee does not explicitly disclose performing a third sensing operation of the bit lines; obtaining a third sensing result of the third sensing operation; and obtaining the second initial program voltage based at least on the first sensing result, the second sensing result, and the third sensing result.
However, in addition to first and second verification, performing third verification in a flash memory device is a well-known technology for a type of memory for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize an additional verification step in flash memory because these conventional technologies are well established in the art of the memory devices.
Allowable Subject Matter
Claims 6-10 and 16-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if overcoming nonstatutory double patenting as indicated above rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached on M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached on 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SUNG IL CHO/Primary Examiner, Art Unit 2825
1 Re independent claims 1, 10 and 19, claims of US Patent recites all the claimed limitations. The various dependent claims are anticipated by/obvious in view of the conflicting patent.
2 To be clearer, performing programming sequence on different word lines is an inherent characteristic of flash memory device. For support, see for example, Li et al. (US 2020/0051620), FIGS 4-8 and accompanying disclosure.
Prosecution Insights