Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
2. The information disclosure statement (IDS) submitted on 06/17/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
5. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
6. Claim(s) 1-3, 8-13 and 18-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over SU et al. (US 2024/0171775) hereinafter “SU” in view of Cao (US 2024/02333192).
As per claim 1, SU discloses an apparatus comprising:
at least one processor; and at least one memory storing instructions that, when executed by the at least one processor (paragraph 0273), cause the apparatus at least to:
determine one or more tiles for the geometry patch data and one or more tiles for the attribute patch data (FIG. 3C; paragraphs 0206-0207);
encapsulate the geometry patch data to the one or more geometry tiles for the geometry patch data, wherein the one or more geometry tiles for the geometry patch data contain the geometry patch data (encapsulating geometry patch data as taught in paragraph 0217; see FIG. 3D);
encapsulate the attribute patch data to the one or more attribute tiles for the attribute patch data, wherein the one or more attribute tiles for the attribute patch data contain the attribute patch data (encapsulating attribute patch data as taught in paragraph 0217; see FIG. 3D);
generate signaling information configured to identify the one or more geometry tiles containing geometry patch data and the one or more attribute tiles containing attribute patch data (see the information identifying the tiles, such as “Tile 0” through “Tile 6” as taught in FIG. 3C and paragraphs 0205-0207); and
create an atlas bitstream containing the one or more geometry tiles, the one or more attribute tiles, and the signaling information (see FIG. 1A and paragraphs 0202 and 0208).
However, SU des not explicitly disclose obtain a presentation mesh sequence; determine, from the presentation mesh sequence, geometry patch data for geometry and attribute patch data for one or more attributes;
In the same field of endeavor, Cao discloses obtain a presentation mesh sequence (FIG. 1, mesh sequence 108); determine, from the presentation mesh sequence, geometry patch data for geometry and attribute patch data for one or more attributes (FIG. 1; paragraphs 0040-0041; Fig. 18 and paragraph 0171, patch geometry component and patch attribute component);
One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to combine the elements taught by SU, with those of Cao, because both references are drawn to the same field of endeavor, because indeed both references are related to 3D or volumetric video coding, and because such a combination represents a mere combination of prior art elements, according to known methods, to yield a predictable result. This rationale is applied to all combination of SU and Cao used in this Office Action unless otherwise noted.
As per claim 2, SU discloses wherein the signaling information comprises a syntax element that maintains tile identifiers in an atlas frame that were parsed with an apparatus, including identifiers signaled with an atlas frame tile identifier syntax element (FIG. 3D; paragraphs 0217-0218).
As per claim 3, SU discloses wherein the signaling information comprises a syntax element that maintains tile identifiers in an atlas frame that were parsed with an apparatus, including identifiers signaled with an atlas frame attribute tile identifier syntax element (FIG. 3D; paragraphs 0217-0218).
As per claim 8, SU discloses wherein the instructions, when executed by the at least one processor, cause the apparatus at least to: signal an atlas tile header type that specifies a coding type of a current atlas tile (FIG. 3D); wherein the atlas tile header type is configured to allow a decoder to differentiate which format of a patch is present, and how to parse the patch (paragraph 0045); wherein a value for the atlas tile header type specifies that the coding type of the current atlas tile comprises a prediction attribute inter atlas tile; wherein another value for the atlas tile header type specifies that the coding type of the current atlas tile comprises an independent attribute intra atlas tile (FIG. 3D and paragraphs 0226-0227).
As per claim 9, SU discloses the apparatus of claim 8, wherein the instructions, when executed by the at least one processor, cause the apparatus at least to:
signal an indication that an atlas tile data unit corresponding to a tile identifier is at an end (i.e., P_END), when: the atlas tile header type comprises the value that specifies that the coding type of the current atlas tile comprises the prediction attribute inter atlas tile, and a mesh patch mode corresponds to inter atlas (see FIG. 3D and paragraph 0226); and
signal an indication that the atlas tile data unit corresponding to the tile identifier is at the end (i.e., I_END), when: the atlas tile header type comprises the another value that specifies that the coding type of the current atlas tile comprises the independent attribute intra atlas tile, and the mesh patch mode corresponds to intra atlas (see FIG. 3D and paragraph 0226).
As per claim 10, SU discloses wherein the instructions, when executed by the at least one processor, cause the apparatus at least to: signal an indication that a mesh patch attribute data unit corresponds to a tile identifier and a patch index, when: the atlas tile header type comprises the value that specifies that the coding type of the current atlas tile comprises the prediction attribute inter atlas tile, and a mesh patch mode is intra prediction; and signal the indication that the mesh patch attribute data unit corresponds to the tile identifier and the patch index, when: the atlas tile header type comprises the another value that specifies that the coding type of the current atlas tile comprises the independent attribute intra atlas tile, and the mesh patch mode is intra independent (see FIG. 3D and paragraphs 0229, 0232-0235).
As per claims 11-13 and 18-20, the claims are directed to a decoding apparatus corresponding to the encoding apparatus of claims 1-3 and 8-10; therefore, arguments analogous to those applied for claims 1-3 and 8-10 are applicable for claims 11-13 and 18-20 (FIG. 1D of SU and FIG. 21 of Cao teach decoding apparatus correspond to the cited encoding apparatus).
As per claim 21, the claim related to a decoding method corresponds to the encoding steps taught in claim 1; therefore, arguments analogous to those applied for claim 1 are applicable for claim 21 (FIG. 1D of SU and FIG. 21 of Cao teach decoding apparatus/method correspond to the cited encoding apparatus/method).
7. Claim(s) 4-7 and 14-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over SU et al. (US 2024/0171775) in view of Cao (US 2024/0233192) in further view of YOON et al. (US 2023/0419557) hereinafter “YOON”.
As per claim 4, SU and Cao discloses disclose the apparatus of claim 1; however, SU or Cao do not explicitly disclose wherein the instructions, when executed by the at least one processor, cause the apparatus at least to: signal a number of bits used to represent an atlas frame tile identifier syntax element corresponding to a geometry tile index; wherein the number of bits used to represent the atlas frame tile identifier syntax element corresponding to the geometry tile index is signaled with an atlas frame tile identifier length syntax element, when the atlas frame tile identifier length syntax element is present; wherein the number of bits used to represent the atlas frame tile identifier syntax element corresponding to the geometry tile index is determined as a ceiling of a logarithm base 2 of a number of tiles in an atlas frame, when the atlas frame tile identifier length syntax element is not present.
In the same field of endeavor, YOON discloses wherein the instructions, when executed by the at least one processor, cause the apparatus at least to: signal a number of bits used to represent an atlas frame tile identifier syntax element corresponding to a geometry tile index; wherein the number of bits used to represent the atlas frame tile identifier syntax element corresponding to the geometry tile index is signaled with an atlas frame tile identifier length syntax element, when the atlas frame tile identifier length syntax element is present; wherein the number of bits used to represent the atlas frame tile identifier syntax element corresponding to the geometry tile index is determined as a ceiling of a logarithm base 2 of a number of tiles in an atlas frame, when the atlas frame tile identifier length syntax element is not present (see paragraph 0554).
One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to combine the elements taught by SU and Cao, with those of YOON, because all references are drawn to the same field of endeavor, because indeed all references are related to 3D or volumetric video coding, and because such a combination represents a mere combination of prior art elements, according to known methods, to yield a predictable result. This rationale is applied to all combination of SU, Cao and YOON used in this Office Action unless otherwise noted.
As per claim 5, arguments analogous to those applied for claim 4 are applicable for claim 5.
As per claim 6, SU and YOON disclose wherein the instructions, when executed by the at least one processor, cause the apparatus at least to: determine a set of values, wherein a number of the values in the set of values comprises a number of attributes (paragraph 0439 of YOON); wherein a value in the set of values corresponds to a number of bits used to represent an atlas frame attribute tile identifier syntax element corresponding to an attribute index and an attribute tile index (paragraph 0554 of YOON), and the set of values comprise values for a number of attribute indexes corresponding to the number of attributes (paragraph 0439 of YOON); determine a length of an atlas tile header syntax element used to specify a tile identifier associated with a current tile as a largest value among: a number of bits used to represent an atlas frame tile identifier syntax element corresponding to a geometry tile index, and the values of the set of values (0554 of YOON); and signal the atlas tile header syntax element used to specify the tile identifier associated with the current tile (see FIG. 3D of SU).
As per claim 7, arguments analogous to those applied for claim 6 are applicable for claim 7.
As per claims 14-17, the claims are directed to a decoding apparatus corresponding to the encoding apparatus of claims 4-7; therefore, arguments analogous to those applied for claims 4-7 are applicable for claims 14-17 (FIG. 1D of SU, FIG. 21 of Cao, and FIG. 16 of YOON teach decoding apparatus correspond to the cited encoding apparatus).
8. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. (US-20220337859, US-20260012639, US-20250117965, US-20210005006, US-20210005016, US-20210227232, US-20220360819, US-20230239451, US-20210090301, US-20230306646, US-20240022765, US-20240406440, US-20240357181, US-20240373063)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED JEBARI whose telephone number is (571)270-7945. The examiner can normally be reached Mon-Fri: 09:00am-06:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chris Kelley can be reached at 571-272-7331. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED JEBARI/Primary Examiner, Art Unit 2482
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