DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Applicant is advised that this Double Patenting rejection will not be held in abeyance. See MPEP § 804(I)(B)(1); 37 CFR § 1.111(b).
Claims 1-13 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-12 of U.S. Patent No. 12,298,826 in view of Yanagidaira (U.S. Patent Number 9,564,185). The conflicting patent claims do not expressly require a memory controller configured to control the semiconductor memory device, and the first signal and second signal are sent from the memory controller. However, Yanagidaira teaches a memory controller (Figure 1, item 300) configured to control the semiconductor memory device (Figure 1, items 400, Column 2, lines 54-61), and the first signal and second signal are sent from the memory controller (Column 2, lines 54-61; i.e., the memory controller 400 transmits a command/address signal [the “first signal”] as well as a data signal [the “second signal”] to the memory devices 400). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Yanagidaira’s teachings of modification of voltage amplitudes in a memory system with the teachings of the conflicting patent, for the purpose of performing a transfer operation at high speed while reducing the power consumption in transferring commands and address and suppressing an increase in power consumption in transferring data (see Yanagidaira, Column 6, lines 9-12).
Instant Claims
Claims of U.S. Patent 12,298,826
1. A memory system comprising: a semiconductor memory device; and a memory controller configured to control the semiconductor memory device, wherein the semiconductor memory device includes: a first pin configured to receive a first signal and a second signal sent from the memory controller, the second signal having a smaller amplitude than the first signal; a first receiving circuit connected to the first pin and configured to output a third signal and a fourth signal having a smaller amplitude than the third signal, the first receiving circuit outputting the third signal based on a comparison between the first signal and a first voltage, the first receiving circuit outputting the fourth signal based on a comparison between the second signal and a second voltage; and a first terminating circuit connected to the first pin and configured to be disabled if the first pin receives the first signal and enabled if the first pin receives the second signal.
1. A semiconductor memory device comprising: a first pin configured to receive a first signal and a second signal having a smaller amplitude than the first signal; a first receiving circuit connected to the first pin and configured to output a third signal and a fourth signal having a smaller amplitude than the third signal, the first receiving circuit outputting the third signal based on a comparison between the first signal and a first voltage, and the first receiving circuit outputting the fourth signal based on a comparison between the second signal and a second voltage; a first terminating circuit connected to the first pin and configured to be disabled if the first pin receives the first signal and enabled if the first pin receives the second signal; a second pin configured to receive a fifth signal and a sixth signal having a smaller amplitude than the fifth signal; a second receiving circuit connected to the second pin and configured to output a seventh signal and an eighth signal having a smaller amplitude than the seventh signal, the second receiving circuit outputting the seventh signal based on a comparison between the fifth signal and the first voltage, and the second receiving circuit outputting the eighth signal based on a comparison between the sixth signal and the second voltage; a second terminating circuit connected to the second pin and configured to be disabled if the second pin receives the fifth signal and enabled if the second pin receives the sixth signal; a third pin configured to receive a ninth signal and a tenth signal having a smaller amplitude than the ninth signal; a third receiving circuit connected to the third pin and configured to output an eleventh signal and a twelfth signal having a smaller amplitude than the eleventh signal, the third receiving circuit outputting the eleventh signal based on a comparison between the ninth signal and the first voltage, and the third receiving circuit outputting the twelfth signal based on a comparison between the tenth signal and the second voltage; and a third terminating circuit connected to the third pin and configured to be disabled if the third pin receives the ninth signal and enabled if the third pin receives the tenth signal. + Yanagidaira, Column 2, lines 54-61
2. The memory system according to claim 1, wherein the second voltage is smaller than the first voltage.
2. The semiconductor memory device according to claim 1, wherein the second voltage is smaller than the first voltage.
3. The memory system according to claim 1, wherein the first terminating circuit includes a first resistor and a first switch connected in series between the first pin and a node for supplying a ground voltage.
3. The semiconductor memory device according to claim 1, wherein the first terminating circuit includes a first resistor and a first switch connected in series between the first pin and a node for supplying a ground voltage.
4. The memory system according to claim 1, wherein the first signal includes a command or an address, and the second signal includes a parameter value or write data.
4. The semiconductor memory device according to claim 1, wherein: the first signal includes a command or an address, and the second signal includes a parameter value or write data.
5. The memory system according to claim 1, wherein the semiconductor memory device further include a first transmitting circuit configured to output a fifth signal and a sixth signal to the memory controller through the first pin, the sixth signal having a smaller amplitude than the fifth signal, wherein the fifth signal includes data indicative of a status, and the sixth signal includes read data.
1. A semiconductor memory device comprising: a first pin configured to receive a first signal and a second signal having a smaller amplitude than the first signal; a first receiving circuit connected to the first pin and configured to output a third signal and a fourth signal having a smaller amplitude than the third signal, the first receiving circuit outputting the third signal based on a comparison between the first signal and a first voltage, and the first receiving circuit outputting the fourth signal based on a comparison between the second signal and a second voltage; a first terminating circuit connected to the first pin and configured to be disabled if the first pin receives the first signal and enabled if the first pin receives the second signal; a second pin configured to receive a fifth signal and a sixth signal having a smaller amplitude than the fifth signal; a second receiving circuit connected to the second pin and configured to output a seventh signal and an eighth signal having a smaller amplitude than the seventh signal, the second receiving circuit outputting the seventh signal based on a comparison between the fifth signal and the first voltage, and the second receiving circuit outputting the eighth signal based on a comparison between the sixth signal and the second voltage; a second terminating circuit connected to the second pin and configured to be disabled if the second pin receives the fifth signal and enabled if the second pin receives the sixth signal; a third pin configured to receive a ninth signal and a tenth signal having a smaller amplitude than the ninth signal; a third receiving circuit connected to the third pin and configured to output an eleventh signal and a twelfth signal having a smaller amplitude than the eleventh signal, the third receiving circuit outputting the eleventh signal based on a comparison between the ninth signal and the first voltage, and the third receiving circuit outputting the twelfth signal based on a comparison between the tenth signal and the second voltage; and a third terminating circuit connected to the third pin and configured to be disabled if the third pin receives the ninth signal and enabled if the third pin receives the tenth signal.
5. The semiconductor memory device according to claim 1, further comprising a first transmitting circuit configured to output the fifth signal and the sixth signal, wherein: the fifth signal includes data indicative of a status, and the sixth signal includes read data.
6. The memory system according to claim 1, wherein the semiconductor memory device further includes a first transmitting circuit configured to output a fifth signal to the memory controller through the first pin, wherein the fifth signal includes status or read data.
6. The semiconductor memory device according to claim 1, further comprising a first transmitting circuit configured to output the fifth signal to the first pin, wherein the fifth signal includes status or read data.
7. The memory system according to claim 6, wherein an output node of the first transmitting circuit is connected, via an NMOS transistor, to a node for supplying a supply voltage.
7. The semiconductor memory device according to claim 6, wherein an output node of the first transmitting circuit is connected, via an NMOS transistor, to a node for supplying a supply voltage.
8. The memory system according to claim 1, wherein the semiconductor memory device further includes: a second pin configured to receive a fifth signal and a sixth signal from the memory controller, the sixth signal having a smaller amplitude than the fifth signal; a second receiving circuit connected to the second pin and configured to output a seventh signal and an eighth signal having a smaller amplitude than the seventh signal, the second receiving circuit outputting the seventh signal based on a comparison between the fifth signal and the first voltage, the second receiving circuit outputting the eighth signal based on a comparison between the sixth signal and the second voltage; a second terminating circuit connected to the second pin and configured to be disabled if the second pin receives the fifth signal and enabled if the second pin receives the sixth signal; a third pin configured to receive a ninth signal and a tenth signal from the memory controller, the tenth signal having a smaller amplitude than the ninth signal; a third receiving circuit connected to the third pin and configured to output an eleventh signal and a twelfth signal having a smaller amplitude than the eleventh signal, the third receiving circuit outputting the eleventh signal based on a comparison between the ninth signal and the first voltage, the third receiving circuit outputting the twelfth signal based on a comparison between the tenth signal and the second voltage; and a third terminating circuit connected to the third pin and configured to be disabled if the third pin receives the ninth signal and enabled if the third pin receives the tenth signal.
1. A semiconductor memory device comprising: a first pin configured to receive a first signal and a second signal having a smaller amplitude than the first signal; a first receiving circuit connected to the first pin and configured to output a third signal and a fourth signal having a smaller amplitude than the third signal, the first receiving circuit outputting the third signal based on a comparison between the first signal and a first voltage, and the first receiving circuit outputting the fourth signal based on a comparison between the second signal and a second voltage; a first terminating circuit connected to the first pin and configured to be disabled if the first pin receives the first signal and enabled if the first pin receives the second signal; a second pin configured to receive a fifth signal and a sixth signal having a smaller amplitude than the fifth signal; a second receiving circuit connected to the second pin and configured to output a seventh signal and an eighth signal having a smaller amplitude than the seventh signal, the second receiving circuit outputting the seventh signal based on a comparison between the fifth signal and the first voltage, and the second receiving circuit outputting the eighth signal based on a comparison between the sixth signal and the second voltage; a second terminating circuit connected to the second pin and configured to be disabled if the second pin receives the fifth signal and enabled if the second pin receives the sixth signal; a third pin configured to receive a ninth signal and a tenth signal having a smaller amplitude than the ninth signal; a third receiving circuit connected to the third pin and configured to output an eleventh signal and a twelfth signal having a smaller amplitude than the eleventh signal, the third receiving circuit outputting the eleventh signal based on a comparison between the ninth signal and the first voltage, and the third receiving circuit outputting the twelfth signal based on a comparison between the tenth signal and the second voltage; and a third terminating circuit connected to the third pin and configured to be disabled if the third pin receives the ninth signal and enabled if the third pin receives the tenth signal.
9. The memory system according to claim 8, wherein the semiconductor memory device further includes: a fourth pin configured to receive a thirteenth signal and a fourteenth signal having a smaller amplitude than the thirteenth signal; a fourth receiving circuit connected to the fourth pin and configured to output a fifteenth signal and a sixteenth signal having a smaller amplitude than the fifteenth signal, the fourth receiving circuit outputting the fifteenth signal based on a comparison between the thirteenth signal and the first voltage, the fourth receiving circuit outputting the sixteenth signal based on a comparison between the fourteenth signal and the second voltage; a fourth terminating circuit connected to the fourth pin and configured to be disabled if the fourth pin receives the thirteenth signal and enabled if the fourth pin receives the fourteenth signal; a fifth pin configured to receive a seventeenth signal and an eighteenth signal having a smaller amplitude than the seventeenth signal; a fifth receiving circuit connected to the fifth pin and configured to output a nineteenth signal and a twentieth signal having a smaller amplitude than the nineteenth signal, the fifth receiving circuit outputting the nineteenth signal based on a comparison between the seventeenth signal and the first voltage, the fifth receiving circuit outputting the twentieth signal based on a comparison between the eighteenth signal and the second voltage; and a fifth terminating circuit connected to the fifth pin and configured to be disabled if the fifth pin receives the seventeenth signal and enabled if the fifth pin receives the eighteenth signal.
8. The semiconductor memory device according to claim 1, further comprising: a fourth pin configured to receive a thirteenth signal and a fourteenth signal having a smaller amplitude than the thirteenth signal; a fourth receiving circuit connected to the fourth pin and configured to output a fifteenth signal and a sixteenth signal having a smaller amplitude than the fifteenth signal, the fourth receiving circuit outputting the fifteenth signal based on a comparison between the thirteenth signal and the first voltage, and the fourth receiving circuit outputting the sixteenth signal based on a comparison between the fourteenth signal and the second voltage; a fourth terminating circuit connected to the fourth pin and configured to be disabled if the fourth pin receives the thirteenth signal and enabled if the fourth pin receives the fourteenth signal; a fifth pin configured to receive a seventeenth signal and an eighteenth signal having a smaller amplitude than the seventeenth signal; a fifth receiving circuit connected to the fifth pin and configured to output a nineteenth signal and a twentieth signal having a smaller amplitude than the nineteenth signal, the fifth receiving circuit outputting the nineteenth signal based on a comparison between the seventeenth signal and the first voltage, and the fifth receiving circuit outputting the twentieth signal based on a comparison between the eighteenth signal and the second voltage; and a fifth terminating circuit connected to the fifth pin and configured to be disabled if the fifth pin receives the seventeenth signal and enabled if the fifth pin receives the eighteenth signal.
10. The memory system according to claim 9, wherein the semiconductor memory device further includes: a first circuit connected to the second receiving circuit and the third receiving circuit and configured to output a twenty-first signal and a twenty-second signal, the first circuit outputting the twenty-first signal and the twenty-second signal based on the seventh signal and the eleventh signal or based on the eighth signal and the twelfth signal; and a latch circuit configured to store, based on the twenty-first signal and the twenty-second signal, data included in the third signal or the fourth signal.
9. The semiconductor memory device according to claim 8, further comprising: a first circuit connected to the second receiving circuit and the third receiving circuit and configured to output a twenty-first signal and a twenty-second signal, the first circuit outputting the twenty-first signal and the twenty-second signal based on the seventh signal and the eleventh signal or based on the eighth signal and the twelfth signal; and a latch circuit configured to store, based on the twenty-first signal and the twenty-second signal, data included in the third signal or the fourth signal.
11. The memory system according to claim 1, wherein the semiconductor memory device further includes a first chip including the first pin, the first receiving circuit, and the first terminating circuit.
10. The semiconductor memory device according to claim 1, further comprising a first chip including the first pin, the first receiving circuit, and the first terminating circuit.
12. The memory system according to claim 1, wherein the semiconductor memory device further includes: a first chip including the first pin and the first receiving circuit; and a second chip including the first terminating circuit.
11. The semiconductor memory device according to claim 1, further comprising: a first chip including the first pin and the first receiving circuit; and a second chip including the first terminating circuit.
13. The memory system according to claim 12, wherein after receipt of a first command which is the first signal and up to receipt of a second command, the first terminating circuit of the semiconductor memory device is in an enabled state for a period where the second chip is receiving a signal for enabling the second chip.
12. The semiconductor memory device according to claim 11, wherein after receipt of a first command which is the first signal and up to receipt of a second command, the first terminating circuit is in an enabled state for a period where the second chip is receiving a signal for enabling the second chip.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 and 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Koo et al. (U.S. Patent Application Publication Number 2017/0222649) and Yanagidaira (U.S. Patent Number 9,564,185).
Regarding Claim 1, Koo discloses a memory system (Figure 15, item 1000) comprising:
a semiconductor memory device (Figure 1, item 100, paragraph 0024; i.e., the system-on-chip may be a memory chip);
wherein the semiconductor memory device includes:
a first pin (Figure 1, item 150) configured to receive a first signal (Figure 1, item DATA) and a second signal (paragraphs 0026 and 0031; i.e., a plurality of data signals are received), the second signal having a smaller amplitude than the first signal (paragraphs 0072-0073; i.e., the interface voltage level VDDH of the data may be of a smaller or larger amplitude depending on whether the ODT is on or off [see Figure 3]; further, the incoming data signals may have various voltage levels ranging from 1.2 to 3.3 volts [paragraph 0025]; therefore, a second incoming signal may have a smaller amplitude [voltage] than a first signal);
a first receiving circuit (Figures 1 and Figure 11, item 130) connected to the first pin and configured to output a third signal (Figure 11, item D_INb) and a fourth signal (Figure 11, item D_INa) having a smaller amplitude than the third signal (paragraphs 0072-0073; i.e., the amplitude of the interface voltage VDDH [which is the level that the “fourth signal” D_INa provides] can be smaller/lower than that of the logic voltage VDDL [which is the level that the “third signal” D_INb provides]), the first receiving circuit outputting the third signal based on a comparison between the first signal and a first voltage (Figure 11, item Vref, paragraph 0084; i.e., the HS buffer 132 outputs the “third signal” D_INb [e.g., a logic 1] based on a comparison of a first incoming voltage level of data D_IO with the reference voltage Vref), the first receiving circuit outputting the fourth signal based on a comparison between the second signal (i.e., a subsequent incoming data signal) and a second voltage (paragraph 0069; i.e., the LS buffer 131 may also compare the incoming voltage level of data D_IO with a reference voltage similar to how the HS buffer 132 does so and output the “fourth signal” D_INa based on the comparison).
Koo does not expressly disclose a memory controller configured to control the semiconductor memory device,
the first signal and second signal are sent from the memory controller,
a first terminating circuit connected to the first pin and configured to be disabled if the first pin receives the first signal and enabled if the first pin receives the second signal (but rather discloses a terminating circuit 162 [Figure 3] that is enabled when a voltage level VDDH is intended to be lowered – see paragraph 0041).
In the same field of endeavor (e.g., modification of voltage amplitudes in a memory system), Yanagidaira teaches a memory controller (Figure 1, item 300) configured to control the semiconductor memory device (Figure 1, items 400, Column 2, lines 54-61),
the first signal and second signal are sent from the memory controller (Column 2, lines 54-61; i.e., the memory controller 400 transmits a command/address signal [the “first signal”] as well as a data signal [the “second signal”] to the memory devices 400),
a first terminating circuit (Figure 2, item 410) connected to the first pin (Figure 2, item 10) and configured to be disabled if the first pin receives the first signal (Column 5, lines 19-29; i.e., the termination circuit 410 is disabled if a command/address signal is received; as shown in Figure 7, the termination circuit 410 [referred to as “POD”] is disabled when the signal has a higher amplitude [VREFq = VCCq + VSSq/2]) and enabled if the first pin receives the second signal (Column 5, lines 46-58; i.e., the termination circuit 410 is enabled if data is received; as shown in Figure 7, the termination circuit 410 [referred to as “POD”] is enabled when the signal has a lower amplitude [VREFq < VCCq + VSSq/2]).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Yanagidaira’s teachings of modification of voltage amplitudes in a memory system with the teachings of Koo, for the purpose of performing a transfer operation at high speed while reducing the power consumption in transferring commands and address and suppressing an increase in power consumption in transferring data (see Yanagidaira, Column 6, lines 9-12).
Regarding Claim 2, Koo discloses wherein the second voltage is smaller than the first voltage (paragraphs 0072-0073 and 0084; i.e., depending on whether the amplitude of voltage VDDL is higher than or lower than the amplitude of voltage VDDH, the reference voltage for the LS buffer 131 may be lower; this is due to the fact that the reference voltage of a smaller amplitude signal must be lower than the reference voltage of a higher amplitude signal, or else the incoming signal will be compared to the wrong reference voltage).
Regarding Claim 3 Yanagidaira teaches wherein the first terminating circuit includes a first resistor (Figure 6, item 412B) and a first switch (Figure 3, item 412A) connected in series between the first pin (Figure 6, item 10) and a node for supplying a ground voltage (Column 6, lines 63-66).
Regarding Claim 4, Yanagidaira teaches wherein the first signal includes a command or an address (Column 5, lines 19-29; i.e., the termination circuit 410 is disabled if a command/address signal is received), and the second signal includes a parameter value or write data (Column 5, lines 46-58; i.e., the termination circuit 410 is enabled if data is received).
Regarding Claim 5, Koo discloses a first transmitting circuit (Figure 1, item 120) configured to output a fifth signal and a sixth signal having a smaller amplitude than the fifth signal (paragraphs 0030 and 0033-0034; i.e., the data can be output at either the VDDL level [the “fifth signal”] or a level-shifted version of the VDDL level [the “sixth signal”]), wherein the fifth signal includes data indicative of a status (paragraph 0038; i.e., one of ordinary skill in the art would recognize that a status would be a type of data of low frequency because there would be no need to transmit status information at a high frequency), and the sixth signal includes read data (paragraph 0038; i.e., the sixth signal, which may have a lower amplitude, may consist of data to be transmitted to the memory).
Regarding Claim 6, Koo discloses a first transmitting circuit (Figure 1, item 120) configured to output a fifth signal to the first pin (Figure 1, item 150), wherein the fifth signal includes status or read data (paragraph 0038).
Regarding Claim 7, Koo discloses wherein an output node (Figure 2, see output of pre-driver 122) of the first transmitting circuit is connected, via an NMOS transistor (Figure 2, item MN2), to a node for supplying a supply voltage (Figure 2; i.e., the node between resistors R1 and R2 of main driver 123a can receive a supply voltage VDDH).
Regarding Claim 11, Yanagidaira teaches a first chip including the first pin, the first receiving circuit, and the first terminating circuit (Figure 2, item 400; i.e., a semiconductor memory chip).
Regarding Claim 12, Yanagidaira teaches a first chip including the first pin and the first receiving circuit (Figure 1, item 100, paragraph 0023; i.e., a system on a chip); and a second chip (Figure 3, item 160) including the first terminating circuit (Figure 3, item 162, paragraph 0039; i.e., a memory chip).
Regarding Claim 13, Yanagidaira teaches wherein after receipt of a first command which is the first signal (Figure 5, items “cmd 80h” – “add #5”) and up to receipt of a second command (Figure 5, “cmd 10h”), the first terminating circuit is in an enabled state (Figure 5; i.e., the POD_EN signal is high, which turns on the terminating circuit 410) for a period (i.e., the period in which data D0-D5 is received) where the second chip is receiving a signal for enabling the second chip (Figure 5, item /CE; i.e., the chip enable signal).
Allowable Subject Matter
Claims 8-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and the Double Patenting rejection discussed above was addressed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 8, the prior art of record does not teach “a second pin configured to receive a fifth signal and a sixth signal having a smaller amplitude than the fifth signal; a second receiving circuit connected to the second pin and configured to output a seventh signal and an eighth signal having a smaller amplitude than the seventh signal, the second receiving circuit outputting the seventh signal based on a comparison between the fifth signal and the first voltage, the second receiving circuit outputting the eighth signal based on a comparison between the sixth signal and the second voltage; a second terminating circuit connected to the second pin and configured to be disabled if the second pin receives the fifth signal and enabled if the second pin receives the sixth signal; a third pin configured to receive a ninth signal and a tenth signal having a smaller amplitude than the ninth signal; a third receiving circuit connected to the third pin and configured to output an eleventh signal and a twelfth signal having a smaller amplitude than the eleventh signal, the third receiving circuit outputting the eleventh signal based on a comparison between the ninth signal and the first voltage, the third receiving circuit outputting the twelfth signal based on a comparison between the tenth signal and the second voltage; and a third terminating circuit connected to the third pin and configured to be disabled if the third pin receives the ninth signal and enabled if the third pin receives the tenth signal.”
All claims that are not specifically addressed are allowable due to a dependency.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure because each reference discloses systems for using terminating circuits in certain amplitude situations.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAISAL M ZAMAN whose telephone number is (571)272-6495. The examiner can normally be reached Monday - Friday, 8 am - 5 pm, alternate Fridays.
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/FAISAL M ZAMAN/ Primary Examiner, Art Unit 2175
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