DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or
nonobviousness.
Claim(s) [ 1, 4-5, 8-11, 14-15, 18-20 ] are rejected under 35 U.S.C. 103 as being unpatentable over [ Nale et al. (US 10795755), hereinafter "Nale", in view of Shaeffer et al. (US 8555116), hereinafter "Shaeffer" ].
As per claim 1, Nale significantly teaches a computer-implemented method for processing scrambled data in a memory device, the method comprising: receiving, from a memory controller, first scrambled data comprising first data to which a first data scrambling operation has been applied (Upon receiving scrambled write data with a write address, the memory module stores the scrambled write data at the write address [Nale PP 0007]);
receiving, from the memory controller, second scrambled data comprising first data to which a second data scrambling operation has been applied, wherein the second scrambled data is different from the first scrambled data (Both seed values are initialized to a common value, and then incremented after processing a read data packet [Nale PP 0013]);
descrambling the [[first]] second scrambled data to generate descrambled data (Described embodiments provide techniques for the memory module controller 20 to descramble write data and store the write data unscrambled [Nale PP 0107]); and
storing the descrambled data in a memory core of the memory device (store the write data unscrambled [Nale PP 0107]).
Nale does not explicitly teach “determining that the first scrambled data includes at least one error;”
However, Shaeffer, in an analogous art, teaches determining that the first scrambled data includes at least one error (The DRAM computes an error-detection code (EDC) based on the address and/or data received from the controller, and transmits this EDC code back to the controller. The controller then determines whether the EDC code is consistent with the previously transmitted address and/or data [Shaeffer PP 0013] DRAM computes an EDC on received data and transmits it back; the controller determines if an error occurred);
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Nale to incorporate Shaeffer's teaching of CRC-based error detection and command retransmission, in order to improve error detection and recovery on the memory interface (The DRAM computes an error-detection code (EDC) based on the address and/or data received from the controller, and transmits this EDC code back to the controller. The controller then determines whether the EDC code is consistent with the previously transmitted address and/or data. [Shaeffer PP 0013], If error detection circuitry 118 detects an error based on the received CRC code, it can cause command generation circuitry 113 to generate and transmit an error indication to DRAM 140 [Shaeffer PP 0026]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Nale's invention.
As per claim 4, Nale does not explicitly teach “wherein determining that the first scrambled data includes at least one error comprises: performing a cyclic redundancy check (CRC) operation on the first scrambled data; and transmitting an error result based associated with the CRC operation.”
However, Shaeffer, in an analogous art, teaches wherein determining that the first scrambled data includes at least one error comprises: performing a cyclic redundancy check (CRC) operation on the first scrambled data (The DRAM computes an error-detection code (EDC) based on the address and/or data received from the controller [Shaeffer PP 0013]); and
transmitting an error result based associated with the CRC operation (If error detection circuitry 118 detects an error based on the received CRC code, it can cause command generation circuitry 113 to generate and transmit an error indication to DRAM 140 [Shaeffer PP 0026]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Nale to incorporate Shaeffer's teaching of CRC-based error detection and command retransmission, in order to improve error detection and recovery on the memory interface (The DRAM computes an error-detection code (EDC) based on the address and/or data received from the controller, and transmits this EDC code back to the controller. The controller then determines whether the EDC code is consistent with the previously transmitted address and/or data. [Shaeffer PP 0013], If error detection circuitry 118 detects an error based on the received CRC code, it can cause command generation circuitry 113 to generate and transmit an error indication to DRAM 140 [Shaeffer PP 0026]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Nale's invention.
As per claim 5, Nale significantly teaches further comprising: loading the descrambled data from the memory core (the memory module controller 20 to descramble write data and store the write data unscrambled and then scramble the stored data to return to a read request [Nale PP 0107]);
applying a third data scrambling operation to the descrambled data to generate third scrambled data (scramble the stored data to return to a read request [Nale PP 0107]); and
transmitting the third scrambled data to the memory controller (In response to a read request, the scrambled data that is stored and sent over the bus to the host memory controller [Nale PP 0007]).
As per claim 8, Nale does not explicitly teach “further comprising: performing a cyclic redundancy check (CRC) operation on the third scrambled data to generate a CRC value; and transmitting the CRC value to the memory controller.”
However, Shaeffer, in an analogous art, teaches further comprising: performing a cyclic redundancy check (CRC) operation on the third scrambled data to generate a CRC value (In the case of a read operation, read/write selector 148 allows the data read from the DRAM core to be sent to CRC generator 150. [Shaeffer PP 0031]); and
transmitting the CRC value to the memory controller (The CRC code is then transmitted via EDC bus 138 to DRAM controller 110 [Shaeffer PP 0021]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Nale to incorporate Shaeffer's teaching of CRC-based error detection and command retransmission, in order to improve error detection and recovery on the memory interface (The DRAM computes an error-detection code (EDC) based on the address and/or data received from the controller, and transmits this EDC code back to the controller. The controller then determines whether the EDC code is consistent with the previously transmitted address and/or data. [Shaeffer PP 0013], If error detection circuitry 118 detects an error based on the received CRC code, it can cause command generation circuitry 113 to generate and transmit an error indication to DRAM 140 [Shaeffer PP 0026]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Nale's invention.
As per claim 9, Nale significantly teaches wherein at least one of the first data scrambling operation, the second data scrambling operation, or the third data scrambling operation is based on a pseudorandom bit sequence, an inversion operation, a shift operation, or a swap operation (Both seed values are initialized to a common value, and then incremented after processing a read data packet [Nale PP 0108] pseudorandom bit sequence (PRBS), includes an inversion bit indicating whether data is inverted [Nale PP 0003]).
As per claim 10, Nale significantly teaches wherein at least one of the first data scrambling operation, the second data scrambling operation, or the third data scrambling operation is based on a logical operation comprising one or more of an exclusive or (XOR) operation, an exclusive not-or (XNOR) operation, an and (AND) operation, a not-and (NAND) operation, an or (OR) operation, or a not-or (NOR) operation (includes an inversion bit indicating whether data is inverted [Nale PP 0003] inverse is a logical NOT operation).
As per claim 11, Nale significantly teaches a system, comprising: a memory controller that: applies a first data scrambling operation to first data to generate first scrambled data, and applies a second data scrambling operation to the first data to generate second scrambled data, wherein the second scrambled data is different from the first scrambled data (Upon receiving scrambled write data with a write address, the memory module stores the scrambled write data at the write address [Nale PP 0007], Both seed values are initialized to a common value, and then incremented after processing a read data packet [Nale PP 0108] Seed increment after each transaction means retransmitted write uses different seed, producing different scrambled data); and
a memory device coupled to the memory controller, and that: receives the first scrambled data from the memory controller (Upon receiving scrambled write data with a write address, the memory module stores the scrambled write data at the write address [Nale PP 0007])
descrambles the second scrambled data to generate descrambled data (the memory module controller 20 to descramble write data and store the write data unscrambled [Nale PP 0107]); and
stores the descrambled data in a memory core of the memory device (store the write data unscrambled [Nale PP 0107]).
Nale does not explicitly teach “determines that the first scrambled data includes at least one error, receives the second scrambled data from the memory controller”
However, Shaeffer, in an analogous art, teaches determines that the first scrambled data includes at least one error (The DRAM computes an error-detection code (EDC) based on the address and/or data received from the controller, and transmits this EDC code back to the controller. The controller then determines whether the EDC code is consistent with the previously transmitted address and/or data [Shaeffer PP 0013]), receives the second scrambled data from the memory controller (If error detection circuitry 118 detects an error based on the received CRC code, it can cause command generation circuitry 113 to generate and transmit an error indication to DRAM 140. ... Subsequently, command generation circuitry 113 re-issues the corresponding memory commands [Shaeffer PP 0026])
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Nale to incorporate Shaeffer's teaching of CRC-based error detection and command retransmission, in order to improve error detection and recovery on the memory interface (The DRAM computes an error-detection code (EDC) based on the address and/or data received from the controller, and transmits this EDC code back to the controller. The controller then determines whether the EDC code is consistent with the previously transmitted address and/or data. [Shaeffer PP 0013], If error detection circuitry 118 detects an error based on the received CRC code, it can cause command generation circuitry 113 to generate and transmit an error indication to DRAM 140 [Shaeffer PP 0026]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Nale's invention.
As per claim 14, Nale does not explicitly teach “wherein, to determine that the first scrambled data includes at least one error, the memory device: performs a cyclic redundancy check (CRC) operation on the first scrambled data; and transmits an error result based associated with the CRC operation.”
However, Shaeffer, in an analogous art, teaches wherein, to determine that the first scrambled data includes at least one error, the memory device: performs a cyclic redundancy check (CRC) operation on the first scrambled data (The DRAM computes an error-detection code (EDC) based on the address and/or data received from the controller [Shaeffer PP 0013]); and
transmits an error result based associated with the CRC operation (If error detection circuitry 118 detects an error based on the received CRC code, it can cause command generation circuitry 113 to generate and transmit an error indication to DRAM 140 [Shaeffer PP 0026]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Nale to incorporate Shaeffer's teaching of CRC-based error detection and command retransmission, in order to improve error detection and recovery on the memory interface (The DRAM computes an error-detection code (EDC) based on the address and/or data received from the controller, and transmits this EDC code back to the controller. The controller then determines whether the EDC code is consistent with the previously transmitted address and/or data. [Shaeffer PP 0013], If error detection circuitry 118 detects an error based on the received CRC code, it can cause command generation circuitry 113 to generate and transmit an error indication to DRAM 140 [Shaeffer PP 0026]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Nale's invention.
As per claim 15, Nale significantly teaches wherein the memory device further: loads the descrambled data from the memory core (the memory module controller 20 to descramble write data and store the write data unscrambled and then scramble the stored data to return to a read request [Nale PP 0107]);
applies a third data scrambling operation to the descrambled data to generate third scrambled data (scramble the stored data to return to a read request [Nale PP 0107]); and
transmits the third scrambled data to the memory controller (In response to a read request, the scrambled data that is stored and sent over the bus to the host memory controller [Nale PP 0007]).
As per claim 18, Nale does not explicitly teach “wherein the memory device further: performs a cyclic redundancy check (CRC) operation on the third scrambled data to generate a CRC value; and transmits the CRC value to the memory controller.”
However, Shaeffer, in an analogous art, teaches wherein the memory device further: performs a cyclic redundancy check (CRC) operation on the third scrambled data to generate a CRC value (In the case of a read operation, read/write selector 148 allows the data read from the DRAM core to be sent to CRC generator 150 [Shaeffer PP 0031]); and
transmits the CRC value to the memory controller (The CRC code is then transmitted via EDC bus 138 to DRAM controller 110. [Shaeffer PP 0021]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Nale to incorporate Shaeffer's teaching of CRC-based error detection and command retransmission, in order to improve error detection and recovery on the memory interface (The DRAM computes an error-detection code (EDC) based on the address and/or data received from the controller, and transmits this EDC code back to the controller. The controller then determines whether the EDC code is consistent with the previously transmitted address and/or data. [Shaeffer PP 0013], If error detection circuitry 118 detects an error based on the received CRC code, it can cause command generation circuitry 113 to generate and transmit an error indication to DRAM 140 [Shaeffer PP 0026]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Nale's invention.
As per claim 19, Nale significantly teaches wherein at least one of the first data scrambling operation, the second data scrambling operation, or the third data scrambling operation is based on a pseudorandom bit sequence, an inversion operation, a shift operation, or a swap operation (Both seed values are initialized to a common value, and then incremented after processing a read data packet [Nale PP 0108], includes an inversion bit indicating whether data is inverted [Nale PP 0003]).
As per claim 20, Nale significantly teaches wherein at least one of the first data scrambling operation, the second data scrambling operation, or the third data scrambling operation is based on a logical operation comprising one or more of an exclusive or (XOR) operation, an exclusive not-or (XNOR) operation, an and (AND) operation, a not-and (NAND) operation, an or (OR) operation, or a not-or (NOR) operation (includes an inversion bit indicating whether data is inverted [Nale PP 0003] "At least one of" is satisfied by inversion (NOT)).
Claim(s) [ 2-3, 6-7, 12-13, 16-17 ] are rejected under 35 U.S.C. 103 as being unpatentable over [Nale, in view of Shaeffer, in further view of Sudhakaran et al. (US 10491238), hereinafter "Sudhakaran" ].
As per claim 2, Nale in view of Shaeffer do not explicitly teach “further comprising, prior to descrambling the second scrambled data, modifying the second scrambled data by performing a decoding operation on the second scrambled data.”
However, Sudhakaran, in an analogous art, teaches further comprising, prior to descrambling the second scrambled data, modifying the second scrambled data by performing a decoding operation on the second scrambled data (The decoding architecture 600 comprises a decoder block 602 for DQ[0] that includes an 8:7 decoder 608 , an XNOR bank 604 , a delay 606 , and an interleave 610 [Sudhakaran PP 0036] decoding received data before further processing (descrambling)).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Nale and Shaeffer to incorporate Sudhakaran’s teaching of MTA/DBI encoding and decoding, in order to reduce ISI and crosstalk on the memory interface (Techniques are disclosed to reduce ISI and crosstalk in PAM-4 signaling systems. These techniques utilize Maximum Transition Avoidance (MTA) to eliminate maximum voltage transitions between PAM-4 symbols on the data lines. The data bus inversion (DBI) line of a PAM-4 bus is utilized to communicate encoded symbols [Sudhakaran PP 0006]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Nale's invention.
As per claim 3, Nale in view of Shaeffer do not explicitly teach “wherein the decoding operation comprises at least one of a maximum transition avoidance (MTA) operation, a data bus inversion (DBI) operation, or a pulse-amplitude modulation version 3 (PAM3) operation.”
However, Sudhakaran, in an analogous art, teaches wherein the decoding operation comprises at least one of a maximum transition avoidance (MTA) operation, a data bus inversion (DBI) operation, or a pulse-amplitude modulation version 3 (PAM3) operation (These techniques utilize Maximum Transition Avoidance (MTA) to eliminate maximum voltage transitions between PAM-4 symbols on the data lines. The data bus inversion (DBI) line of a PAM-4 bus is utilized to communicate encoded symbols [Sudhakaran PP 0006]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Nale and Shaeffer to incorporate Sudhakaran’s teaching of MTA/DBI encoding and decoding, in order to reduce ISI and crosstalk on the memory interface (Techniques are disclosed to reduce ISI and crosstalk in PAM-4 signaling systems. These techniques utilize Maximum Transition Avoidance (MTA) to eliminate maximum voltage transitions between PAM-4 symbols on the data lines. The data bus inversion (DBI) line of a PAM-4 bus is utilized to communicate encoded symbols [Sudhakaran PP 0006]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Nale's invention.
As per claim 6, Nale in view of Shaeffer do not explicitly teach “further comprising, prior to transmitting the third scrambled data, modifying the third scrambled data by performing an encoding operation on the third scrambled data.”
However, Sudhakaran, in an analogous art, teaches further comprising, prior to transmitting the third scrambled data, modifying the third scrambled data by performing an encoding operation on the third scrambled data (The PAM-4 symbol encoder 104 receives a burst to encode from the processing core 114 and performs encoding on that burst. The PAM-4 transmitter 108 transmits the encoded burst [Sudhakaran PP 0019]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Nale and Shaeffer to incorporate Sudhakaran’s teaching of MTA/DBI encoding and decoding, in order to reduce ISI and crosstalk on the memory interface (Techniques are disclosed to reduce ISI and crosstalk in PAM-4 signaling systems. These techniques utilize Maximum Transition Avoidance (MTA) to eliminate maximum voltage transitions between PAM-4 symbols on the data lines. The data bus inversion (DBI) line of a PAM-4 bus is utilized to communicate encoded symbols [Sudhakaran PP 0006]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Nale's invention.
As per claim 7, Nale in view of Shaeffer do not explicitly teach “wherein the encoding operation comprises at least one of a maximum transition avoidance (MTA) operation, a data bus inversion (DBI) operation, or a pulse-amplitude modulation version 3 (PAM3) operation.”
However, Sudhakaran, in an analogous art, teaches wherein the encoding operation comprises at least one of a maximum transition avoidance (MTA) operation, a data bus inversion (DBI) operation, or a pulse-amplitude modulation version 3 (PAM3) operation (These techniques utilize Maximum Transition Avoidance (MTA) to eliminate maximum voltage transitions between PAM-4 symbols on the data lines. The data bus inversion (DBI) line of a PAM-4 bus is utilized to communicate encoded symbols [Sudhakaran PP 0006] "At least one of" is satisfied by MTA or DBI teachings).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Nale and Shaeffer to incorporate Sudhakaran’s teaching of MTA/DBI encoding and decoding, in order to reduce ISI and crosstalk on the memory interface (Techniques are disclosed to reduce ISI and crosstalk in PAM-4 signaling systems. These techniques utilize Maximum Transition Avoidance (MTA) to eliminate maximum voltage transitions between PAM-4 symbols on the data lines. The data bus inversion (DBI) line of a PAM-4 bus is utilized to communicate encoded symbols [Sudhakaran PP 0006]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Nale's invention.
As per claim 12, Nale in view of Shaeffer do not explicitly teach “wherein, prior to descrambling the second scrambled data, the memory device modifies the second scrambled data by performing a decoding operation on the second scrambled data.”
However, Sudhakaran, in an analogous art, teaches wherein, prior to descrambling the second scrambled data, the memory device modifies the second scrambled data by performing a decoding operation on the second scrambled data (The decoding architecture 600 comprises a decoder block 602 for DQ[0] that includes an 8:7 decoder 608 , an XNOR bank 604 , a delay 606 , and an interleave 610 [Sudhakaran PP 0031]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Nale and Shaeffer to incorporate Sudhakaran’s teaching of MTA/DBI encoding and decoding, in order to reduce ISI and crosstalk on the memory interface (Techniques are disclosed to reduce ISI and crosstalk in PAM-4 signaling systems. These techniques utilize Maximum Transition Avoidance (MTA) to eliminate maximum voltage transitions between PAM-4 symbols on the data lines. The data bus inversion (DBI) line of a PAM-4 bus is utilized to communicate encoded symbols [Sudhakaran PP 0006]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Nale's invention.
As per claim 13, Nale in view of Shaeffer do not explicitly teach “wherein the decoding operation comprises at least one of a maximum transition avoidance (MTA) operation, a data bus inversion (DBI) operation, or a pulse-amplitude modulation version 3 (PAM3) operation.”
However, Sudhakaran, in an analogous art, teaches wherein the decoding operation comprises at least one of a maximum transition avoidance (MTA) operation, a data bus inversion (DBI) operation, or a pulse-amplitude modulation version 3 (PAM3) operation (These techniques utilize Maximum Transition Avoidance (MTA) to eliminate maximum voltage transitions between PAM-4 symbols on the data lines. The data bus inversion (DBI) line of a PAM-4 bus is utilized to communicate encoded symbols [Sudhakaran PP 0006]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Nale and Shaeffer to incorporate Sudhakaran’s teaching of MTA/DBI encoding and decoding, in order to reduce ISI and crosstalk on the memory interface (Techniques are disclosed to reduce ISI and crosstalk in PAM-4 signaling systems. These techniques utilize Maximum Transition Avoidance (MTA) to eliminate maximum voltage transitions between PAM-4 symbols on the data lines. The data bus inversion (DBI) line of a PAM-4 bus is utilized to communicate encoded symbols [Sudhakaran PP 0006]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Nale's invention.
As per claim 16, Nale in view of Shaeffer do not explicitly teach “wherein, prior to transmitting the third scrambled data, the memory device modifies the third scrambled data by performing an encoding operation on the third scrambled data.”
However, Sudhakaran, in an analogous art, teaches wherein, prior to transmitting the third scrambled data, the memory device modifies the third scrambled data by performing an encoding operation on the third scrambled data (The PAM-4 symbol encoder 104 receives a burst to encode from the processing core 114 and performs encoding on that burst. The PAM-4 transmitter 108 transmits the encoded burst. [Sudhakaran PP 0018]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Nale and Shaeffer to incorporate Sudhakaran’s teaching of MTA/DBI encoding and decoding, in order to reduce ISI and crosstalk on the memory interface (Techniques are disclosed to reduce ISI and crosstalk in PAM-4 signaling systems. These techniques utilize Maximum Transition Avoidance (MTA) to eliminate maximum voltage transitions between PAM-4 symbols on the data lines. The data bus inversion (DBI) line of a PAM-4 bus is utilized to communicate encoded symbols [Sudhakaran PP 0006]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Nale's invention.
As per claim 17, Nale in view of Shaeffer do not explicitly teach “wherein the encoding operation comprises at least one of a maximum transition avoidance (MTA) operation, a data bus inversion (DBI) operation, or a pulse-amplitude modulation version 3 (PAM3) operation.”
However, Sudhakaran, in an analogous art, teaches wherein the encoding operation comprises at least one of a maximum transition avoidance (MTA) operation, a data bus inversion (DBI) operation, or a pulse-amplitude modulation version 3 (PAM3) operation (These techniques utilize Maximum Transition Avoidance (MTA) to eliminate maximum voltage transitions between PAM-4 symbols on the data lines. The data bus inversion (DBI) line of a PAM-4 bus is utilized to communicate encoded symbols [Sudhakaran PP 0006]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Nale and Shaeffer to incorporate Sudhakaran’s teaching of MTA/DBI encoding and decoding, in order to reduce ISI and crosstalk on the memory interface (Techniques are disclosed to reduce ISI and crosstalk in PAM-4 signaling systems. These techniques utilize Maximum Transition Avoidance (MTA) to eliminate maximum voltage transitions between PAM-4 symbols on the data lines. The data bus inversion (DBI) line of a PAM-4 bus is utilized to communicate encoded symbols [Sudhakaran PP 0006]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Nale's invention.
Conclusion
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/KAREEM FUAD ALHWAMDEH/Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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