Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka (US 2004/0034621)
In regards to claims 1 and 11, Tanaka teaches
An apparatus for indirect memory access using a shared object pointer, the apparatus (fig. 3, p57-65, teaches after the creation of objects the object reference (i.e. pointer) can be stored in a table and the program can use the entries in the table (i.e. pointers) to then access the object (i.e. indirectly)
comprising:
receive a request for a memory allocation for an object, the request specifying use of the shared pointer; (p57-65 fig. 3 step S1 issue an object creation command that is then accessed via a reference (pointer)
identify a memory address that is part of memory, accessible via the interface, used to fulfill the memory allocation; (p57-65 fig. 3 steps S2-S3 an empty region of memory is retrieved (i.e. identified), secured and the object is created.
writing a pointer to the memory address into a shared memory location, the shared memory location being accessible by a host and the memory device; (fig. 3, p53-65, teaches after the creation of objects the object reference (i.e. pointer) can be stored in a table and the program can use the entries in the table (i.e. pointers) to then access the object (i.e. indirectly). the table (of pointers) can be stored in the mapping management table 103 and is shared/transferred to the other mapping management table 203)
receive a request from the host for the object, the request including the memory address as read by the host from the pointer; and return data, retrieved via the interface, at the memory used to fulfill the memory allocation based on the request from the host. (fig. 3, p6 steps s5 and s6 create and then send the reference to the object to the requesting application (host), which the host can then use to access the object. fig. 7, p75-82 also teaches that another host can request access to the object (i.e. request transfer) and the object is moved to it’s local shared memory heap, the references (pointers) are updated and then returned to the application program to then be used)
Tanaka doesn’t explicitly teach
an interface to a memory device; and
processing circuitry that, when in operation, is configured to:
However, it clearly suggests that data is being stored/shared/transferred and that this storing/sharing/transferred is being done is being done by something that is capable of interfacing with where the data is stored (i.e. memory device). Therefore it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have incorporated an interface to a memory device such that that interface was able to access/manipulate the objects in the memory via pointers and to be able to transfer/reproduce these shared objects and pointers between two different system. The motivation for such a modification is that this allows multiple applications (i.e. hosts) to be able to share and manipulate the same set of data in a coordinated fashion.
In regards to claims 2 and 12, Tanaka makes obvious
move data in the memory used to fulfill the memory allocation to second memory, the second memory corresponding to a second memory address; and update the pointer to point to the second memory address. (fig. 7 and 20 details transfers to a second memory, where afterwards the pointers are updated to point to the new location (see steps s25, s26 for fig. 7 and steps s85-86 of fig. 20)
In regards to claims 3 and 13, Tanaka makes obvious
wherein the processing circuitry is configured to update a set of requests pending at the memory device for the memory address to the second memory address. (fig. 7 and 20 details transfers to a second memory, where afterwards the pointers are updated to point to the new location (see steps s25, s26 for fig. 7 and steps s85-86 of fig. 20)
In regards to claims 4 and 14, Tanaka makes obvious
wherein, to update the set of requests, the processing circuitry is configured to rewrite the memory address to the second memory address. (fig. 7 and 20 details transfers to a second memory, where afterwards the pointers are updated to point to the new location (see steps s25, s26 for fig. 7 and steps s85-86 of fig. 20)
In regards to claims 5 and 15, Tanaka makes obvious
wherein, to update the set of requests, the processing circuitry is configured to translate the memory address to the second memory address when executing members of the set of requests. (fig. 7 steps s27-28 and fig. 20 step s87, the updated (second) memory addresses (which have been translated from the original addresses) are returned to the application program so that it may access the objects at the new location.)
In regards to claims 6 and 16, Tanaka make not explicitly teach
wherein the processing circuitry is configured to deny a second memory request based on receiving a second memory request from the host after the data in the memory used to fulfill the memory allocation has begun moving and before the pointer is updated to point to the second memory address.
However, fig. 15 shows that object state data 374 and update flag information 364 are kept for each of the shared objects. Furthermore, fig. 7 sets the internal states for the region prior to starting the transfer and updates them after the reproduction of the object (see steps s24-25). Therefore it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention that continued access to an object that has not been transferred would be denied and/or delayed either based on the internal states of the objects, or the fact that the program/host can’t retrieve the correct addresses(pointers) until the transfer is completed. The motivation for making such a modification is that this prevents the system from accessing incomplete and/or corrupted data that is in the process of being transferred.
In regards to claims 7 and 17, Tanaka makes obvious
wherein the shared memory location is subject to a cache coherence mechanism between the host and the memory device. (fig. 15, object state data 374 and block update flags are associated with objects stored in the shared heap memory regions. p88-92 and fig. 10 shows that this information can be used to keep the data is both sets of shared memory coherent (i.e. differences/updates are transfered)
In regards to claims 8 and 18, Tanaka makes obvious
wherein the memory used to fulfill the memory allocation is tiered memory, the tiered memory including multiple tiers of performance. (fig. 13 shows each system has its own shared heap region, where one is local to the current application and the other is remoted (i.e. tiered, as the local memory will always be able to be accesses faster). The system will transfer data to the “local” shared memory of the requester (for example see fig. 20).
In regards to claims 9 and 19, Tanaka may not explicitly teach
wherein the pointer is maintained in a data structure, the data structure including a lock for the object, the lock specifying which of the host or the memory device can update the pointer in the data structure.
However, Tanaka shows in fig. 15, object state data 374 and block update flags are associated with objects stored in the shared heap memory regions. It is also within the knowledge and the skill of one of ordinary skill in the art to be able to applying locking semaphores on shared data so as to prevent inadvertent access/corruption of data. Therefore it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have used their skill/knowledge to implement sufficient locks/semaphores for shared data. The motivation for such modifications is that the can prevent inadvertent access/corruption of data, and could have been implemented this modification and achieved predictable results.
In regards to claims 10 and 20, Tanaka makes obvious
wherein the data structure includes a size for the object. (fig. 15, shared object information includes a block size 362 and number of blocks 361 included in the object)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Kuznetsov (US 2009/0037807) details the use of pointers for sharing data in shared memory regions.
Ritchie (US 2020/0104196) details methods of shared memory allocation.
Tsirkin (US 2020/0409759) details methods for using shared memory and addresses for accomplishing zero copy message receptions.
Doshi (US 2018/0095906) details hardware based shared memory coherency systems/methods.
Berggren (US 5,247,616) teaches the use of addresses in shared memory spaces as part of DMA memory accesses and transfers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON W BLUST whose telephone number is (571)272-6302. The examiner can normally be reached 12-8:30 EST.
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/JASON W BLUST/ Primary Examiner, Art Unit 2132
