DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Application filed April 9, 2025.
Claims 1-20 are pending. Claims 1, 11 and 20 are independent.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 5-8, 11-12 and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoo (U.S. 2017/0068481).
Regarding independent claim 1, Yoo discloses A method of operating a memory device (see Abstract), the method comprising:
during first program loops (Fig. 12: 1st PGM), applying first consecutive program pulses to a first word line of the memory device (Fig. 12: Vpgm11-Vpgm1n), wherein the first consecutive program pulses increase sequentially with a first step voltage (Fig. 12: ΔVpgm1);
during second program loops (Fig. 12: 2nd PGM), applying second consecutive program pulses to the first word line (Fig. 12: Vpgm21-Vpgm2m), wherein the second consecutive program pulses increase sequentially with a second step voltage (Fig. 12: ΔVpgm2), and wherein the first step voltage is larger than the second step voltage (see Fig. 12: ΔVpgm2 is less than ΔVpgm1); and
during third program loops (Fig. 12: 3rd PGM), applying third consecutive program pulses to the first word line (Fig. 12: Vpgm31-Vpgm3k), wherein the third consecutive program pulses increase sequentially with a third step voltage (Fig. 12: ΔVpgm3), and wherein the second step voltage is larger than the third step voltage (see Fig. 12: ΔVpgm3 is less than ΔVpgm2).
Regarding claim 2, Yoo discloses wherein the second program loops are after the first program loops and the third program loops are after the second program loops (see Fig. 12).
Regarding claim 5, Yoo discloses performing a first program operation on a first memory cell coupled to the first word line to program the first memory cell to a first intermediate state, wherein the first program operation comprises at least one of the first program loops, the second program loops, or the third program loops (Fig. 11 shows a 1st step PGM and a 2nd step PGM to program the cell to an intermediate state, e.g. P11, P21, P22, P23); and
performing a second program operation on the first memory cell to program the first memory cell from the first intermediate state to a first target state (Fig. 11 shows a 3RD step PGM to program the cell to a tighter state i.e. “target state”, P31, P32, P33).
Regarding claim 6, Yoo discloses wherein the first memory cell is a quad-level cell (QLC) (see page 6, par. 0080).
Regarding claim 7, Yoo discloses wherein the first intermediate state is one of 8 intermediate states and the first target state is one of 16 target states (For a 4-bit data programmed per memory cell, i.e. QLC has 16 distinct threshold voltage states and has 8 threshold voltage margin between any one program state, see pages 5-6, par. 0078-0080).
Regarding claim 8, Yoo discloses wherein the first intermediate state is one of 16 intermediate states and the first target state is one of 16 target states (For a 4-bit data programmed per memory cell, i.e. QLC has 16 distinct threshold voltage states, see pages 5-6, par. 0078-0080).
Regarding independent claim 11, Yoo discloses a method of operating a memory device (see Abstract), the method comprising:
performing a first program operation on a first memory cell of the memory device to program the first memory cell to a first intermediate state (Fig. 11 shows a 1st step PGM and a 2nd step PGM to program the cell to an intermediate state, e.g. P11, P21, P22, P23), wherein the first program operation comprises:
during first program loops (Fig. 12: 1st PGM), applying first consecutive program pulses to a first word line coupled to the first memory cell (Fig. 12: Vpgm11-Vpgm1n), wherein the first consecutive program pulses increase sequentially with a first step voltage (Fig. 12: ΔVpgm1); and
during second program loops (Fig. 12: 2nd PGM), applying second consecutive program pulses to the first word line (Fig. 12: Vpgm21-Vpgm2m), wherein the second consecutive program pulses increase sequentially with a second step voltage (Fig. 12: ΔVpgm2); and
performing a second program operation on the first memory cell to program the first memory cell from the first intermediate state to a first target state (Fig. 11 shows a 3RD step PGM to program the cell to a tighter state i.e. “target state”, P31, P32, P33).
Regarding claim 12, Yoo discloses wherein the first step voltage is larger than the second step voltage (see Fig. 12: ΔVpgm2 is less than ΔVpgm1).
Regarding claim 19, Yoo discloses wherein the first memory cell is a quad-level cell (QLC) (see page 6, par. 0080).
Regarding independent claim 20, Yoo discloses a memory device (Fig. 1), comprising:
a memory array (Fig. 3: 121);
word lines coupled to the memory array (Fig. 4: WLs); and
a peripheral circuit coupled to the word lines and configured to perform an operation (Fig. 3: 122-126), wherein the operation comprises:
during first program loops (Fig. 12: 1st PGM), applying first consecutive program pulses to a first word line of the word lines (Fig. 12: Vpgm11-Vpgm1n), wherein the first consecutive program pulses increase sequentially with a first step voltage (Fig. 12: ΔVpgm1);
during second program loops (Fig. 12: 2nd PGM), applying second consecutive program pulses to the first word line (Fig. 12: Vpgm21-Vpgm2m), wherein the second consecutive program pulses increase sequentially with a second step voltage (Fig. 12: ΔVpgm2), and wherein the first step voltage is larger than the second step voltage (see Fig. 12: ΔVpgm2 is less than ΔVpgm1); and
during third program loops after the second program loops (Fig. 12: 3rd PGM), applying third consecutive program pulses to the first word line (Fig. 12: Vpgm31-Vpgm3k), wherein the third consecutive program pulses increase sequentially with a third step voltage (Fig. 12: ΔVpgm3), and wherein the second step voltage is larger than the third step voltage (see Fig. 12: ΔVpgm3 is less than ΔVpgm2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 13-14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Yoo (U.S. 2017/0068481) in view of Cho et al. (U.S. 2018/0211715; hereinafter “Cho”).
Regarding claim 4, Yoo discloses the limitations with respect to claim 1.
However, Yoo is silent with respect to wherein the third consecutive program pulses are larger than the second consecutive program pulses, and the second consecutive program pulses are larger than the first consecutive program pulses.
Similar to Yoo, Cho teaches a method of operating a memory device comprising firs program loops applying first consecutive program pulses (Fig. 4A: Loop2), second program loops applying second consecutive program pulses (Fig. 4A: Loop3) and third program loops applying third consecutive program pulses (Fig. 4A: Loop4).
Furthermore, Cho teaches wherein the third consecutive program pulses are larger than the second consecutive program pulses, and the second consecutive program pulses are larger than the first consecutive program pulses (see Fig. 4A).
Since Cho and Yoo are from the same field of endeavor, the teachings described by Cho would have been recognized in the pertinent art of Yoo.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Cho with the teachings of Yoo for the purpose of improve data stored reliability, see Cho’s page 1, par. 0005.
Regarding claim 13, Yoo discloses the limitations with respect to claim 12.
However, Yoo is silent with respect to wherein the first program operation further comprises during third program loops after second program loops, applying third consecutive program pulses to the first word line, wherein the third consecutive program pulses increase sequentially with a third step voltage, and wherein the second step voltage is larger than the third step voltage.
Similar to Yoo, Cho teaches a method of operating a memory device comprising a first program operation (Fig. 4A).
Furthermore, Cho teaches wherein the first program operation further comprises during third program loops after second program loops (Fig. 4A: Loop4 after Loop3), applying third consecutive program pulses to the first word line (Fig. 4A: PP1_4-PP3_4), wherein the third consecutive program pulses increase sequentially with a third step voltage, and wherein the second step voltage is larger than the third step voltage (Fig. 4A shows the program pulses of Loop4 increases by a step voltage that is smaller than the step voltage applied to the program pulses of Loop3).
Since Cho and Yoo are from the same field of endeavor, the teachings described by Cho would have been recognized in the pertinent art of Yoo.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Cho with the teachings of Yoo for the purpose of improve data stored reliability, see Cho’s page 1, par. 0005.
Regarding claim 14, Yoo in combination with Cho teaches the limitations with respect to claim 13.
Furthermore, Cho teaches wherein the second program loops are after the first program loops and the third program loops are after the second program loops (see Fig. 4A).
Regarding claim 16, Yoo in combination with Cho teaches the limitations with respect to claim 13.
Furthermore, Cho teaches wherein the third consecutive program pulses are larger than the second consecutive program pulses, and wherein the second consecutive program pulses are larger than the first consecutive program pulses (see Fig. 4A).
Allowable Subject Matter
Claims 3, 9-10, 15 and 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 3, there is no teaching or suggestion in the prior art of record to provide the recited first set voltage is 1.3 times of a predetermined step voltage, the second step voltage is 1.2 times of the predetermined step voltage, and the third step voltage is 1.1 times of the predetermined step voltage.
With respect to claim 9, there is no teaching or suggestion in the prior art of record to provide the recited step of performing the second program operation comprises applying fourth consecutive program pulses to the first word line, and wherein the fourth consecutive program pulses increase sequentially with a fourth step voltage.
With respect to claim 15, there is no teaching or suggestion in the prior art of record to provide the recited first step voltage is 1.3 times of a predetermined step voltage, the second step voltage is 1.2 times of the predetermined step voltage, and the third step voltage is 1.1 times of the predetermined step voltage.
With respect to claim 17, there is no teaching or suggestion in the prior art of record to provide the recited step of performing the second program operation comprises applying fourth consecutive program pulses to the first word line, and wherein the fourth consecutive program pulses increase sequentially with a fourth step voltage.
Conclusion
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/Alfredo Bermudez Lozada/ Primary Examiner, Art Unit 2825
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