DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-5, 7-9, 11-13, 15-17, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Artieri (US 2018/0314586 A1).
For claim 1, Artieri teaches a method, comprising: reading first data from a dynamic random-access memory (DRAM) array (see [0035] and other locations); performing an on-die error correction code operation on the first data to obtain corrected data and a first error type associated with the corrected data (see abstract, [0092], [0033], tables 1, and other locations: embodiment in which everything, including ECC, is in one ASIC/die; multiple types of ECC are supported including hamming types, and depending on bit word length), wherein the first error type is determined from more than three error types (see [0033], table 1: 9 bit ECC, 14-bit ECC, W3C, etc.); outputting, via one or more data (DQ) pins during a burst interval, the corrected data (see [0034-0035]); and outputting, via one or more error information pins during the burst interval, the first error type (see [0034-0035]: ECC pin: outputs an error of a type).
For claim 3, Artieri teaches the limitations of claim 1 for the reasons above and further teaches performing the on-die error correction code operation comprises: correcting a quantity of errors in the first data to obtain the corrected data, wherein the first error type comprises one of a corrected single bit error or a corrected multi-bit error in accordance with the quantity of errors (see [0033]: multiple single bit errors correction).
For claim 4 Artieri teaches the limitations of claim 1 for the reasons above and further teaches receiving a read command, wherein reading the first data from the DRAM array is responsive to the read command (see [0035]: read burst follows read command).
For claim 5 Artieri teaches the limitations of claim 1 for the reasons above and further teaches reading parity bits associated with the first data from the DRAM array, wherein performing the on-die error correction code operation is in accordance with the parity bits. (see abstract, [0004]: ECC parity matrix)
For claim 7 Artieri teaches the limitations of claim 1 for the reasons above and further teaches the first error type comprises one of a no errors, a corrected single bit error, a corrected multi-bit error, or an uncorrectable error. (see rational and locations pointed to in rejection to claim 3: this is a subgroup)
For claim 8 Artieri teaches the limitations of claim 1 for the reasons above and further teaches the corrected data comprises the first data, and wherein the first error type comprises a no error state (see figure 5 table).
For claims 9, 11-13, 15-16, the claims recite essentially similar limitations as claims 1, 3-5, and 7-8 respectively. Claims 9, 11-13, 15-16 are a memory device.
For claim 17, Artieri teaches a method, comprising: transmitting a read command to read first data from a dynamic random-access memory (DRAM) array (see [0003], [0014]:SoC sends commands to DRAM); receiving, via one or more data (DQ) pins during a burst interval, corrected data associated with the first data (see [0031], [0034-0035]: burst read and write DQ plus paritybits); and receiving, via one or more error information pins during the burst interval, a first error type associated with the corrected data, wherein the first error type is determined from more than three error types (see rejection to claim 1).
For claim 19, Artieri teaches the limitations of claim 17 for the reasons above and further teaches the first error type comprises one of a no error type, a corrected single bit error type, a corrected multi-bit error type, or an uncorrectable error type (see [0033]: multiple single bit errors correction).
For claim 20, Artieri teaches the limitations of claim 17 for the reasons above and further teaches the corrected data comprises the first data, and wherein the first error type comprises a no error type (see figure 5 table).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Artieri (US 2018/0314586 A1), and further in view of Spencer (US 2004/0193808 A1).
For claim 2,
Artieri teaches the limitations of claim 1 for the reasons above.
Artieri does not explicitly teach “storing the first error type associated with the corrected data in a register in accordance with performing the on-die error correction code operation”
However, Spencer teaches storing the first error type associated with the corrected data in a register in accordance with performing the on-die error correction code operation (see [0012], [0095], and other locations: error enable register stores/signals error types)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Artieri to include “storing the first error … code operation”, as taught by Spencer, because each one of Artieri and Spencer teach burst and ECC operations in DRAMs therefore they are analogous arts and because error types are needed to be stored to enable or disable them as needed (see [0012], [0095], and other locations).
For claim 10,
The claim recites essentially similar limitations as claims 2. Claim 10 is a memory device
Claims 6, 14, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Artieri (US 2018/0314586 A1), and further in view of Houston (US 6,493,656 B1).
For claim 6,
Artieri teaches the limitations of claim 1 for the reasons above.
Artieri does not explicitly teach “the first error type is encoded to four or more bits”
However, Houston teaches the first error type is encoded to four or more bits (see column 5 lies 54-58: Reed-Solomon has more than four encoded bits)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Artieri to include “the first error type is encoded to four or more bits”, as taught by Houston, because each one of Artieri and Houston teach burst and ECC operations in DRAMs therefore they are analogous arts and because great majority of ECC encoders encode many bits (see column 5 lies 54-58:).
For claim 14,
The claim recites essentially similar limitations as claims 6. Claim 14 is a memory device
For claim 18,
Artieri teaches the limitations of claim 17 for the reasons above.
The claim further recites essentially similar limitations as claims 6.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YAIR LEIBOVICH whose telephone number is (571)270-3796. The examiner can normally be reached 8:00am-5:00pm.
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/YAIR LEIBOVICH/Primary Examiner, Art Unit 2114
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