Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al., US PGPUB 20230268910 hereinafter referenced as Lin in view of Abe, US PGPUB 20090231241.
As to claim 1, Lin discloses a driver disposed in a display panel, the driver including: a plurality of stages (e.g., plurality stages of fig. 2E),
at least one stage of the plurality of stages comprising: an input circuit which transfers an input signal to a first node ([0139] inverter INV1m has an input coupled to the intermediate node 212); and
inverters which generate an output signal based on a voltage of the first node ([0030] inverter INV2m has an input coupled to the data output 213 of the master latch circuit 210),
at least one of the inverters including: a p-type metal-oxide-semiconductor transistor including a first active region ([0041] In some embodiments, the transistor T3 is a PMOS transistor, and the transistor T4 is an NMOS transistor. A source/drain of the transistor T3 is coupled to a source/drain of the transistor T4 at the node ml_ax. Another source/drain of the transistor T3 and another source/drain of the transistor T4 are coupled to an output of the inverter INV2m); and
an n-type metal-oxide-semiconductor transistor including a second active region, wherein the p-type metal-oxide-semiconductor transistor and the n-type metal-oxide- semiconductor transistor are connected in series between a line transferring a relatively high gate voltage and a line transferring a relatively low gate voltage ([0112] In the inverter configuration in FIG. 8A, the transistors PM, NM are coupled in series between the power supply voltage VDD and the ground voltage VSS).
Lin does not specifically disclose the first active region of the p-type metal-oxide-semiconductor transistor includes a material different from a material of the second active region of the n-type metal-oxide-semiconductor transistor.
However, using different material for p-type and n-type semiconductor transistor is well known in the art. For example, Abe discloses the first active region of the p-type metal-oxide-semiconductor transistor includes a material different from a material of the second active region of the n-type metal-oxide-semiconductor transistor ([0012] with regard to the OS, the n-type semiconductor and the p-type semiconductor that have a high mobility are made of different materials).
Therefore, it would have been obvious to one of ordinary skill in the art to modify the disclosure of Lin to further include Abe’s method of using p-type and n-type semiconductor with different materials, in order to reduce the cost of manufacturing.
As to claim 20, Lin discloses an electronic device comprising: a processor configured to provide input image data ([0036] The shift register is used for outputting the initial scan signal to the input terminal of the inverter and the first control terminal of the line drive signal enhancement circuit); and
a display device configured to receive the input image data from the processor, and to display an image based on the input image data, the display device comprising: a display panel including a plurality of pixels ([0098] According to an embodiment of the present disclosure, the display panel is further provided with a pixel driving circuit in the display area, and the pixel driving circuit includes a data writing unit, a storage capacitor and a driving transistor);
a data driver which provides data signals to the plurality of pixels (e.g., master latch circuit 210, fig. 2A);
a gate driver which provides gate signals to the plurality of pixels (e.g., slave latch circuit 220, fig. 2E);
an emission driver which provides emission signals to the plurality of pixels; and
a controller which controls the data driver, the gate driver and the emission driver (e.g., IC device 100, fig. 1),
wherein at least one of the gate driver and the emission driver includes a plurality of stages (e.g., plurality stages of fig. 2E), and
wherein at least one stage of the plurality of stages comprising: an input circuit which transfers an input signal to a first node (e.g., input circuit 240, fig. 2); and
inverters which generate an output signal corresponding to one of the gate signals or one of the emission signals based on a voltage of the first node ([0030] inverter INV2m has an input coupled to the data output 213 of the master latch circuit 210),
wherein at least one of the inverters includes a p-type metal-oxide-semiconductor transistor and an n-type metal-oxide-semiconductor transistor connected in series between a line transferring a relatively high gate voltage and a line transferring a relatively low gate voltage ([0041] In some embodiments, the transistor T3 is a PMOS transistor, and the transistor T4 is an NMOS transistor. A source/drain of the transistor T3 is coupled to a source/drain of the transistor T4 at the node ml_ax. Another source/drain of the transistor T3 and another source/drain of the transistor T4 are coupled to an output of the inverter INV2m).
Lin does not specifically disclose the first active region of the p-type metal-oxide-semiconductor transistor includes a material different from a material of the second active region of the n-type metal-oxide-semiconductor transistor.
However, using different material for p-type and n-type semiconductor transistor is well known in the art. For example, Abe discloses the first active region of the p-type metal-oxide-semiconductor transistor includes a material different from a material of the second active region of the n-type metal-oxide-semiconductor transistor ([0012] with regard to the OS, the n-type semiconductor and the p-type semiconductor that have a high mobility are made of different materials).
Therefore, it would have been obvious to one of ordinary skill in the art to modify the disclosure of Lin to further include Abe’s method of using p-type and n-type semiconductor with different materials, in order to reduce the cost of manufacturing.
As to claim 2, the combination of Lin and Abe discloses the driver of claim 1. The combination further discloses the first active region of the p-type metal-oxide-semiconductor transistor includes polycrystalline silicon, and wherein the second active region of the n-type metal-oxide-semiconductor transistor includes at least one of an oxide semiconductor, an organic semiconductor and amorphous silicon ([0114] The gate region 810 includes a conductive material, such as, polysilicon).
As to claim 3, the combination of Lin and Abe discloses the driver of claim 1. The combination further discloses the first active region of the p-type metal-oxide semiconductor transistor and the second active region of the n-type metal-oxide- semiconductor transistor are disposed in different layers, respectively, disposed at different heights, respectively, from a substrate of the display panel (Lin, In at least one embodiment, one or more of the electrical connections 311-314 comprise one or more metal layers on a front side of a substrate of an IC device, and/or one or more backside metal layers on a back side of the substrate, as described with respect to FIGS. 8B-8C).
As to claim 4, the combination of Lin and Abe discloses the driver of claim 1. The combination further discloses the n-type metal-oxide-semiconductor transistor includes a top gate disposed above the second active region, and a bottom gate disposed below the second active region, wherein a second relatively low gate voltage different from the relatively low gate voltage is applied to the bottom gate of the n-type metal-oxide-semiconductor transistor, and wherein the second relatively low gate voltage is lower than the relatively low gate voltage (Lin, [0042] The inverter INV1m comprises a PMOS transistor (not numbered) and an NMOS transistor (not numbered) serially coupled between a power supply voltage VDD and a ground voltage VSS).
As to claim 5, the combination of Lin and Abe discloses the driver of claim 1. The combination further discloses the n-type metal-oxide-semiconductor transistor includes a top gate disposed above the second active region, and a bottom gate disposed below the second active region, and wherein the bottom gate of the n-type metal-oxide-semiconductor transistor is connected to the top gate of the n-type metal-oxide-semiconductor transistor (Lin, e.g., TG1m (top gate) and TG2m (bottom gate) fig. 2A).
As to claim 6, the combination of Lin and Abe discloses the driver of claim 1. The combination further discloses the input circuit includes: a first p-type metal-oxide-semiconductor transistor which transfers the input signal to the first node in response to a first clock signal; and a first n-type metal-oxide-semiconductor transistor which transfers the input signal to the first node in response to a second clock signal having a phase different from a phase of the first clock signal (Lin, [0030] The master latch circuit 210 further comprises a first clock input 216 coupled, by an electrical connection 218, to receive a first clock signal clkb from a clock output 231 of the clock circuit 230, and coupled to corresponding gates of the transmission gates TG1m, TG2m).
As to claim 7, the combination of Lin and Abe discloses the driver of claim 6. The combination further discloses the first p-type metal-oxide-semiconductor transistor includes a gate receiving the first clock signal, a first terminal receiving the input signal, and a second terminal connected to the first node, and wherein the first n-type metal-oxide-semiconductor transistor includes a gate receiving the second clock signal, a first terminal receiving the input signal, and a second terminal connected to the first node (Lin, [0030] The master latch circuit 210 further comprises a second clock input 217 coupled, by an electrical connection 219, to receive a second clock signal clkbb from a clock output 232 of the clock circuit 230, and coupled to corresponding further gates of the transmission gates TG1m, TG2m).
As to claim 8, the combination of Lin and Abe discloses the driver of claim 1. The combination further discloses the at least one stage further comprises: a first capacitor which holds the voltage of the first node, and wherein the first capacitor includes a first electrode connected to the line transferring the relatively high gate voltage, and a second electrode connected to the first node (Lin, 0027] Examples of transistors include, but are not limited to, metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high voltage transistors, high frequency transistors, p-channel and/or n-channel field effect transistors (PFETs/NFETs), FinFETs, and planar MOS transistors with raised sources/drains).
As to claim 9, the combination of Lin and Abe discloses the driver of claim 1. The combination further discloses the inverters include: a first complementary metal-oxide-semiconductor inverter which provides an inverted voltage to a second node by inverting the voltage of the first node; and a second complementary metal-oxide-semiconductor inverter which generates the output signal by inverting a voltage of the second node, wherein the first complementary metal-oxide-semiconductor inverter includes: a second p-type metal-oxide-semiconductor transistor including a gate connected to the first node, a first terminal connected to the line transferring the relatively high gate voltage, and a second terminal connected to the second node; and a second n-type metal-oxide-semiconductor transistor including a gate connected to the first node, a first terminal connected to the line transferring the relatively low gate voltage, and a second terminal connected to the second node, and wherein the second complementary metal-oxide-semiconductor inverter includes: a third p-type metal-oxide-semiconductor transistor including a gate connected to the second node, a first terminal connected to the line transferring the relatively high gate voltage, and a second terminal connected to an output node at which the output signal is output; and a third n-type metal-oxide-semiconductor transistor including a gate connected to the second node, a first terminal connected to the line transferring the relatively low gate voltage, and a second terminal connected to the output node (Lin, [0051] The PMOS transistors having the gates correspondingly coupled to receive signals SE, D are serially coupled between the power supply voltage VDD and the node 243. The circuit 242 comprises four NMOS transistors (not numbered) having gates correspondingly coupled to receive signals SE, SI, D, seb. The NMOS transistors having the gates correspondingly coupled to receive signals SE, SI are serially coupled between the ground voltage VSS and the node 244. The NMOS transistors having the gates correspondingly coupled to receive signals D, seb are serially coupled between the ground voltage VSS and the node 244).
As to claim 10, the combination of Lin and Abe discloses the driver of claim 1. The combination further discloses the at least one stage further comprises: a fourth p-type metal-oxide-semiconductor transistor which transfers the relatively high gate voltage to the first node in response to a global reset signal, and wherein the fourth p-type metal-oxide-semiconductor transistor includes a gate receiving the global reset signal, a first terminal connected to the line transferring the relatively high gate voltage, and a second terminal connected to the first node (Lin, [0046] The inverter INV1s comprises a PMOS transistor (not numbered) and an NMOS transistor (not numbered) serially coupled between the power supply voltage VDD and the ground voltage VSS. The gates of the PMOS and NMOS transistors are coupled to the node sl_a).
As to claim 11, the combination of Lin and Abe discloses the driver of claim 1. The combination further discloses the n-type metal-oxide-semiconductor transistor includes a bottom gate, wherein the at least one stage further comprises: a charge pump circuit which generates a bottom gate voltage applied to the bottom gate based on the relatively low gate voltage and a clock signal, and wherein the charge pump circuit includes: a fifth p-type metal-oxide-semiconductor transistor including a gate connected to a third node, a first terminal connected to the bottom gate, and a second terminal connected to the third node; a sixth p-type metal-oxide-semiconductor transistor including a gate connected to the line transferring the relatively low gate voltage, a first terminal connected to the third node, and a second terminal connected to the line transferring the relatively low gate voltage; a second capacitor including a first electrode connected to the third node, and a second electrode; and a seventh p-type metal-oxide-semiconductor transistor including a gate connected to the third node, a first terminal connected to the second electrode of the second capacitor, and a second terminal receiving the clock signal (Lin, [0048] A source/drain of the transistor CK1 and a source/drain of the transistor CK2 are coupled together to define an output of the first inverter where the first clock signal clkb is generated to be supplied to the master latch circuit and the slave latch circuit. The second inverter comprises a PMOS transistor CK3 and an NMOS transistor CK4 serially coupled between the power supply voltage VDD and the ground voltage VSS. Gates of the transistors CK3, CK4 are coupled to the output of the first inverter to receive the first clock signal clkb).
As to claim 12, the combination of Lin and Abe discloses the driver of claim 1. The combination further discloses the inverters include: a first complementary metal-oxide-semiconductor inverter which provides an inverted voltage to a second node by inverting the voltage of the first node; and a second complementary metal-oxide-semiconductor inverter which generates the output signal by inverting a voltage of the second node, and wherein the at least one stage further comprises: an eighth p-type metal-oxide-semiconductor transistor including a gate connected to the first node, a first terminal connected to an output node at which the output signal is output, and a second terminal connected to the line transferring the relatively low gate voltage (Lin, [0094] Compared to the selection circuit 260, the selection circuit 460 comprises an additional inverter, and the inverters of the selection circuit 460 are configured to correspondingly output signals seb1, seb2 both of which are inverted to the selection signal SE).
As to claim 13, the combination of Lin and Abe discloses the driver of claim 1. The combination further discloses the inverters include: a first complementary metal-oxide-semiconductor inverter which provides an inverted voltage to a second node by inverting the voltage of the first node; and a p-type metal-oxide-semiconductor inverter which outputs the relatively high gate voltage as the output signal when a voltage of the second node has a relatively low level, wherein the at least one stage further comprises: a p-type metal-oxide-semiconductor boosting buffer which outputs the relatively low gate voltage as the output signal when the voltage of the first node has a relatively low level, and wherein the p-type metal-oxide-semiconductor boosting buffer includes: a third capacitor including a first electrode connected to an output node at which the output signal is output, and a second electrode connected to a fourth node; a ninth p-type metal-oxide-semiconductor transistor including a gate connected to the fourth node, a first terminal connected to the output node, and a second terminal connected to the 5 line transferring the relatively low gate voltage; and a tenth p-type metal-oxide-semiconductor transistor including a gate connected to the line transferring the relatively low gate voltage, a first terminal connected to the first node, and a second terminal connected to the fourth node (Lin, [0040] ) transistor. Other transistor configurations are within the scopes of various embodiments. A source/drain of the transistor T1 is coupled to a source/drain of the transistor T2 at a node ml_ax corresponding to the intermediate node 212. Another source/drain of the transistor T1 and another source/drain of the transistor T2 are correspondingly coupled to circuits 241, 242, correspondingly at nodes 243, 244. The circuits 241, 242 constitute a multiplexer corresponding to the multiplexer MUX, as described herein).
As to claim 14, the combination of Lin and Abe discloses the driver of claim 1. The combination further discloses the inverters include: a first complementary metal-oxide-semiconductor inverter which provides an inverted voltage to a second node by inverting the voltage of the first node; and a second complementary metal-oxide-semiconductor inverter which generates the output signal by inverting a voltage of the second node, and wherein the at least one stage further comprises: a p-type metal-oxide-semiconductor boosting buffer which outputs the relatively low gate voltage as the output signal when the voltage of the first node has a relatively low level (Lin, 0041] The transmission gate TG2m comprises a pair of transistors T3, T4 having gates correspondingly coupled to receive the first clock signal clkb and the second clock signal clkbb. In some embodiments, the transistor T3 is a PMOS transistor, and the transistor T4 is an NMOS transistor. A source/drain of the transistor T3 is coupled to a source/drain of the transistor T4 at the node ml_ax. Another source/drain of the transistor T3 and another source/drain of the transistor T4 are coupled to an output of the inverter INV2m).
As to claim 15, the combination of Lin and Abe discloses the driver of claim 1. The combination further discloses the inverters include: a first complementary metal-oxide-semiconductor inverter which provides an inverted voltage to a second node by inverting the voltage of the first node; and a second complementary metal-oxide-semiconductor inverter which generates the output signal by inverting a voltage of the second node, wherein the at least one stage further comprises: a third complementary metal-oxide-semiconductor inverter which generates a carry signal by inverting the voltage of the second node, and wherein the third complementary metal-oxide-semiconductor inverter includes: an eleventh p-type metal-oxide-semiconductor transistor including a gate connected to the second node, a first terminal connected to the line transferring the relatively high gate voltage, and a second terminal connected to a carry node at which the carry signal is output; and a fourth n-type metal-oxide-semiconductor transistor including a gate connected to the second node, a first terminal connected to the line transferring the relatively low gate voltage, and a second terminal connected to the carry node (Lin, [0046] The inverter INV1s comprises a PMOS transistor (not numbered) and an NMOS transistor (not numbered) serially coupled between the power supply voltage VDD and the ground voltage VSS. The gates of the PMOS and NMOS transistors are coupled to the node sl_a. A source/drain of the PMOS transistor is coupled to a source/drain of the NMOS transistor at a node sl_bx corresponding to the data output 223 of the slave latch circuit).
As to claim 16, the combination of Lin and Abe discloses the driver of claim 15. The combination further discloses the at least one stage further comprises: a p-type metal-oxide-semiconductor boosting buffer which outputs the relatively low gate voltage as the output signal when the voltage of the first node has a relatively low level, and wherein the p-type metal-oxide-semiconductor boosting buffer includes: a third capacitor including a first electrode connected to the carry node at which the carry signal is output, and a second electrode connected to a fourth node; a ninth p-type metal-oxide-semiconductor transistor including a gate connected to the fourth node, a first terminal connected to an output node at which the output signal is output, and a second terminal connected to the line transferring the relatively low gate voltage; and a tenth p-type metal-oxide-semiconductor transistor including a gate connected to the line transferring the relatively low gate voltage, a first terminal connected to the first node, and a second terminal connected to the fourth node (Abe, [0054] Further, the capacitor C has one end connected to the gate terminals of the first thin film transistor and the second thin film transistor (L-TFT and D-TFT) and has the other end connected to the source terminals of the first thin film transistor and the second thin film transistor. A second line DL supplies a drive signal of the light emitting device).
As to claim 17, the combination of Lin and Abe discloses the driver of claim 1. The combination further discloses the inverters include: a first complementary metal-oxide-semiconductor inverter which provides an inverted voltage to a second node by inverting the voltage of the first node; and a p-type metal-oxide-semiconductor inverter which outputs the relatively high gate voltage as the output signal when a voltage of the second node has a relatively low level, and wherein the at least one stage further comprises: a p-type metal-oxide-semiconductor boosting buffer which outputs the relatively low gate voltage as the output signal when the voltage of the first node has a relatively low level; and a third complementary metal-oxide-semiconductor inverter which generates a carry signal by inverting the voltage of the second node (Abe, [0049] The organic EL device enables light emission at low voltage and with high efficiency by laminating organic layers serving as a light emitting layer between an anode electrode and a cathode electrode according to functions thereof and by increasing the number of functional laminated layers of the organic layers).
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Yu et al., US PGPUB 20210167090 hereinafter referenced as Yu.
As to claim 18, Lin discloses a driver disposed in a display panel, the driver including: a plurality of stages (e.g., plurality stages of fig. 2E),
at least one stage of the plurality of stages comprising: an input circuit which transfers an input signal to a first node ([0139] inverter INV1m has an input coupled to the intermediate node 212); and
inverters which generate an output signal based on a voltage of the first node, at least one of the inverters includes: a p-type metal-oxide-semiconductor transistor ([0030] inverter INV2m has an input coupled to the data output 213 of the master latch circuit 210); and
an n-type metal-oxide-semiconductor transistor including: an active region ([0041] In some embodiments, the transistor T3 is a PMOS transistor, and the transistor T4 is an NMOS transistor. A source/drain of the transistor T3 is coupled to a source/drain of the transistor T4 at the node ml_ax. Another source/drain of the transistor T3 and another source/drain of the transistor T4 are coupled to an output of the inverter INV2m);
a top gate disposed above the active region (e.g., TG1m, fig. 2A); and
a bottom gate disposed below the active region (e.g., TG2m, fig. 2A),
wherein the p-type metal-oxide-semiconductor transistor and the n-type metal-oxide- semiconductor transistor are connected in series between a line transferring a relatively high gate voltage and a line transferring a relatively low gate voltage (Lin, [0042] The inverter INV1m comprises a PMOS transistor (not numbered) and an NMOS transistor (not numbered) serially coupled between a power supply voltage VDD and a ground voltage VSS).
Lin does not specifically disclose the p-type metal-oxide-semiconductor transistor and the n-type metal-oxide-semiconductor transistor having active regions.
However, Yu discloses the p-type metal-oxide-semiconductor transistor and the n-type metal-oxide-semiconductor transistor having active regions ([0012] with regard to the OS, the n-type semiconductor and the p-type semiconductor that have a high mobility are made of different materials).
Therefore, it would have been obvious to one of ordinary skill in the art to modify the disclosure of Lin to further include Abe’s method of using p-type and n-type semiconductor with active regions, in order to improve circuit performance and reduce circuit area.
19. The driver of claim 18, wherein an active region of the p-type metal-oxide- semiconductor transistor includes a material different from a material of the active region of the n-type metal-oxide-semiconductor transistor (Yu, [0046] The first active region 112 may be defined along the first direction X. The first active region 112 may be defined by a deep trench DT. The first active region 112 may be a region in which a p-type transistor is formed. The first active region 112 may include a well region doped with, e.g., n-type impurities).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kang et al., US PGPUB 20210328582 discloses a master latch circuit, including a first p-type transistor, a first n-type transistor, and a second n-type transistor connected in series; a first node connected to the first p-type transistor and the first n-type transistor, and a NAND circuit configured to receive a signal of the first node and a clock signal and output a result of a NAND operation to a second node, wherein a gate of the first p-type transistor is connected to the second node.
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/SAHLU OKEBATO/Primary Examiner, Art Unit 2625 1/8/2026