DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
2. Claims 1-17 are presented for examination.
Abstract
3. The abstract of the disclosure is acceptable for examination purposes.
Oath Declaration
4. The Oath complies with all the requirements set forth in MPEP 602 and therefore is accepted.
Drawings
5. The drawings received on 04/10/2025 are acceptable for examination purposes.
Information Disclosure Statement
6. The references listed in the information disclosure statement (IDS) submitted on 04/10/2025 have been considered. The submission complies with the provisions of 37 CFR 1.97. Form PTO- 1449 is signed and attached hereto.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
7. Claims 1-17 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
As per claim 1:
The claim recites “A system, comprising: a memory device; and a test device configured to generate a first glitch signal before a write operation of the memory device, wherein the test device is further configured to determine, based on write data of the write operation, whether bits of read data outputted in a read operation of the memory device are moved toward a first side to generate a test result indicating a disturbance to the write operation induced by the first glitch signal, wherein when the bits of the read data are moved toward the first side, compared with the write data, at least one mismatched bit between the read data and the write data has a logic high value.”
At step 2A prong 1:
The claim recites the following limitations directed to an abstract idea “determine, ---, whether bits of read data outputted in a read operation of the memory device are moved toward a first side to generate a test result indicating a disturbance to the write operation induced by the first glitch signal, wherein when the bits of the read data are moved toward the first side, compared with the write data, at least one mismatched bit between the read data and the write data has a logic high value,” as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the human mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
At Step 2A, Prong Two:
This judicial exception is not integrated into a practical application. In particular, the claim recites additional elements of “generate a first glitch signal before a write operation of the memory device” because is a generic computer function of data mere data generating. These extra-solution activities do not provide practical application.
At step 2B:
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional elements “a memory device,” and “a test device” are well-understood, routine and conventional activities used as a tool to perform the processes and do not result in the claim as a whole amounting to significantly more than the abstract idea. In Berkheimer v. HP, Inc., 881 F.3d 1360, 125 USPQ2d 1649 (Fed. Cir. 2018), in which the patentee claimed methods for parsing and evaluating data using a computer processing system. See the prior arts Nguyen et al. (U.S. PN: 2022/019919) in Fig. 1, and Kwon et al. US 20180374555 A1 in Fig. 1 teach well known elements. As discussed above with respect to integration of the abstract idea into a practical application. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. The claim is not patent eligible.
As per claim 8:
The claim recites “A system comprising: a memory device; and a test device that is configured to output a glitch signal and a differential data strobe signal pair to the memory device, wherein the memory device is configured to latch data for a write operation according to the differential data strobe signal pair, wherein the test device is further configured to compare write data corresponding to the write operation and read data outputted in a read operation of the memory device to determine whether the memory device is disturbed by the glitch signal, wherein when bits of the read data are moved toward a first side, compared with the write data, at least one mismatched bit between the read data and the write data has a logic high value.”
At step 2A prong 1:
The claim recites the following limitations directed to an abstract idea “compare write data corresponding to the write operation and read data outputted in a read operation of the memory device to determine whether the memory device is disturbed by the glitch signal, wherein when bits of the read data are moved toward a first side, compared with the write data, at least one mismatched bit between the read data and the write data has a logic high value,” as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the human mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
At Step 2A, Prong Two:
This judicial exception is not integrated into a practical application because the additional limitations of “output a glitch signal and a differential data strobe signal pair to the memory device,” “latch data for a write operation according to the differential data strobe signal pair” because are a generic computer function of data mere data outputting and latching. These extra-solution activities do not provide practical application.
At step 2B:
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional elements “a memory device,” and “a test device” are well-understood, routine and conventional activities used as a tool to perform the processes and do not result in the claim as a whole amounting to significantly more than the abstract idea. In Berkheimer v. HP, Inc., 881 F.3d 1360, 125 USPQ2d 1649 (Fed. Cir. 2018), in which the patentee claimed methods for parsing and evaluating data using a computer processing system. See the prior arts Nguyen et al. (U.S. PN: 2022/019919) in Fig. 1, and Kwon et al. US 20180374555 A1 in Fig. 1 teach well known elements. As discussed above with respect to integration of the abstract idea into a practical application. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. The claim is not patent eligible.
As per claim 13:
The claim recites “A method, comprising: generating a write data signal, a glitch signal and a control signal to a memory device; latching data from the write data signal for a write operation in response to at least one of the glitch signal and the control signal; performing a read operation to generate a read data signal after the write operation; and determining, based on write data signal, whether bits of the read data signal are moved toward a first side to generate a test result indicating a disturbance to the write operation induced by the glitch signal, wherein when the bits of the read data signal are moved toward a first side, compared with the write data signal, at least one mismatched bit between the read data signal and the write data signal has a logic high value.”
At step 2A prong 1:
The claim recites the following limitations directed to an abstract idea “determining, based on write data signal, whether bits of the read data signal are moved toward a first side to generate a test result indicating a disturbance to the write operation induced by the glitch signal, wherein when the bits of the read data signal are moved toward a first side, compared with the write data signal, at least one mismatched bit between the read data signal and the write data signal has a logic high value,” as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the human mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
At Step 2A, Prong Two:
This judicial exception is not integrated into a practical application because the additional limitations of “generating a write data signal, a glitch signal and a control signal to a memory device; latching data from the write data signal for a write operation in response to at least one of the glitch signal and the control signal; performing a read operation to generate a read data signal after the write operation.” The additional limitations do not integrate the abstract idea into a practical application because are a generic computer function of data generating, latching, and performing a read operation. These extra-solution activities do not provide practical application.
At step 2B:
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. Therefore, the claim is not patent eligible.
Dependent claims 2-7, 9-12, and 14-17 recite are more additional limitations without significantly more. Therefore, the claims recite no additional limitation that would amount to significantly more than the abstract idea defined in its respective independent claim. Accordingly, for the reasons provided above, claims 1-17 are directed to an abstract idea, hence, not patent eligible under 35 USC 101
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
8. Claims 1-17 are non-provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-16 of patent application No: US 12,308,086 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-17 of the present application are substantially equivalent to claims 1-16 of the reference application as shown in the chart and explanation below.
Instant Application No. 19/175,689
U.S Patent No. 12,308,086
Claim 1.
A system, comprising: a memory device; and a test device configured to generate a first glitch signal before a write operation of the memory device,
wherein the test device is further configured to determine, based on write data of the write operation, whether bits of read data outputted in a read operation of the memory device are moved toward a first side to generate a test result indicating a disturbance to the write operation induced by the first glitch signal,
wherein when the bits of the read data are moved toward the first side, compared with the write data, at least one mismatched bit between the read data and the write data has a logic high value.
Claim 2.
The system of claim 1, wherein the test device is operatively coupled to first and second data strobe pins of the memory device which are configured to receive a differential data strobe signal pair.
Claim 1.
A system, comprising: a memory device; and a test device that is operatively coupled to the memory device and configured to transmit a plurality of glitch signals and a plurality of control signals after the plurality of glitch signals for a write operation of the memory device according to a data signal,
wherein the test device is further configured to determine, based on write data of the data signal, whether bits of read data outputted in a read operation of the memory device are moved toward a first side to generate a test result indicating a disturbance to the write operation induced by the plurality of glitch signals,
wherein when the bits of the read data are moved toward the first side, compared with the write data, at least one mismatched bit between the read data and the write data has a logic high value.
Claim 3.
The system of claim 2, wherein the test device is further configured to output the first glitch signal to the first data strobe pin and a second glitch signal, inverted from the first glitch signal, to the second data strobe pin.
Claim 2.
The system of claim 1, wherein the test device is operatively coupled to first and second data strobe pins of the memory device which are configured to receive a differential data strobe signal pair wherein the differential data strobe signal pair comprises the plurality of control signals, wherein the test device is further configured to output a first glitch signal of the plurality of glitch signals to the first data strobe pin and a second glitch signal, inverted from the first glitch signal, to the second data strobe pin.
Claim 4.
The system of claim 3, wherein in the write operation, the memory device is configured to latch data of data signal of the write operation in response to at least three edges that are in the first glitch signal and in a control signal to the first data strobe pin.
Claim 3.
The system of claim 1, wherein in the write operation, the memory device is configured to latch data of the data signal in response to at least three edges that are in a first glitch signal of the plurality of glitch signals and in a first control signal of the plurality of control signals.
Claim 5.
The system of claim 1, wherein the first glitch signal has a first voltage level in a first interval and a second voltage level in a second interval after the first interval.
Claim 4.
The system of claim 3, wherein the first glitch signal has a first voltage level in a first interval and a second voltage level in a second interval after the first interval.
Claim 6.
The system of claim 5, wherein when a ratio between the first and second intervals ranges from 0.025 to 0.075, the read data are inconsistent with the write data.
Claim 5.
The system of claim 4, wherein when a ratio between the first and second intervals ranges from 0.025 to 0.075, the read data are inconsistent with the write data
Claim 7.
The system of claim 5, wherein when a ratio between the first and second intervals ranges from 0.15 to 0.25, the read data are consistent with the write data.
Claim 6.
The system of claim 4, wherein when a ratio between the first and second intervals ranges from 0.15 to 0.25, the read data are consistent with the write data.
Claim 8.
A system comprising: a memory device; and a test device that is configured to output a glitch signal and a differential data strobe signal pair to the memory device,
wherein the memory device is configured to latch data for a write operation according to the differential data strobe signal pair, wherein the test device is further configured to compare write data corresponding to the write operation and read data outputted in a read operation of the memory device to determine whether the memory device is disturbed by the glitch signal,
wherein when bits of the read data are moved toward a first side, compared with the write data, at least one mismatched bit between the read data and the write data has a logic high value.
Claim 7.
A system comprising: a memory device comprising an input/output circuit; and a test device that is configured to output a differential data strobe signal pair to first and second data strobe pins of the memory device,
wherein the test device is further configured to output first and second glitch signals to the first and second data strobe pins, and output a plurality of control signals to the first and second data strobe pins after the first and second glitch signals are output, wherein the input/output circuit is configured to latch, in response to the first and second glitch signals and the plurality of control signals, data for a write operation of a memory device, wherein the test device is further configured to compare write data corresponding to the write operation and read data outputted in a read operation of the memory device to determine whether the memory device is disturbed by the first and second glitch signals,
wherein when the bits of the read data are moved toward a first side, compared with the write data, at least one mismatched bit between the read data and the write data has a logic high value.
Claim 9.
The system of claim 8, wherein the test device is further configured to generate the signals at a first time and generate a control signal at a second time after the first time for the write operation.
Claim 8.
The system of claim 7, wherein the test device is further configured to generate the first and second glitch signals at a first time and generate the plurality of control signal at a second time after the first time.
Claim 10.
The system of claim 9, wherein the memory device comprises an input/output circuit configured to latch the data at a third time after the second time.
Claim 9.
The system of claim 8, wherein the input/output circuit latches the data at a third time after the second time.
Claim 11.
The system of claim 8, wherein the glitch signal has a first voltage level in a first interval and has a second voltage level greater than the first voltage level in a second interval after the first interval, wherein when a ratio between the first and second intervals is greater than 0.125, the read data are consistent with the write data.
Claim 10.
The system of claim 7, wherein the first glitch signal has a first voltage level in a first interval and has a second voltage level greater than the first voltage level in a second interval after the first interval, wherein when a ratio between the first and second intervals is greater than 0.125, the read data are consistent with the write data.
Claim 12.
The system of claim 8, wherein the glitch signal has different voltage levels in a first interval and in a second interval after the first interval, wherein when a ratio between the first and second intervals is smaller than 0.1, the write data are inconsistent with the read data.
Claim 11.
The system of claim 7, wherein the first glitch signal has different voltage levels in a first interval and in a second interval after the first interval, wherein when a ratio between the first and second intervals is smaller than 0.1, the write data are inconsistent with the read data.
Claim 13.
A method, comprising: generating a write data signal, a glitch signal and a control signal to a memory device;
latching data from the write data signal for a write operation in response to at least one of the glitch signal and the control signal;
performing a read operation to generate a read data signal after the write operation; and determining, based on write data signal,
whether bits of the read data signal are moved toward a first side to generate a test result indicating a disturbance to the write operation induced by the glitch signal,
wherein when the bits of the read data signal are moved toward a first side, compared with the write data signal, at least one mismatched bit between the read data signal and the write data signal has a logic high value.
Claim 12.
A method, comprising: generating a write data signal to a first pin of a memory device; generating a glitch signal and a control signal to a second pin of the memory device;
latching data from the write data signal for a write operation in response to at least one of the glitch signal and the control signal;
performing a read operation to generate a read data signal; and determining, based on write data signal,
whether bits of the read data signal are moved toward a first side to generate a test result indicating a disturbance to the write operation induced by the glitch signal,
wherein when the bits of the read data signal are moved toward a first side, compared with the write data signal, at least one mismatched bit between the read data signal and the write data signal has a logic high value.
Claim 14.
The method of claim 13, wherein a duration of the glitch signal is shorter than a clock period of the memory device.
Claim 13.
The method of claim 12, wherein a duration of the glitch signal is shorter than a clock period of the memory device.
Claim 15.
The method of claim 13, the glitch signal has a first voltage level in a first interval and has a second voltage in a second interval different from the first interval.
Claim 14.
The method of claim 12, the glitch signal has a first voltage level in a first interval and has a second voltage in a second interval different from the first interval.
Claim 16.
The method of claim 15, when the second interval is greater than the first interval, the read data signal is inconsistent with the write data signal.
Claim 15.
The method of claim 14, when the second interval is greater than the first interval, the read data signal is inconsistent with the write data signal.
Claim 17.
The method of claim 15, further comprising: displaying, by a display device, the write data signal and the read data signal for a comparison thereof.
Claim 16.
The method of claim 14, further comprising: displaying, by a display device, the write data signal and the read data signal for a comparison thereof.
From the table above, claims 1-16 of the reference application ‘086 contain every limitation of claims 1-17 of the instant application except the feature of “generate a first glitch signal before a write operation.” However, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, that the reference application can include generate a first glitch signal before a write operation since teaches transmit a plurality of glitch signals.
This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the generate a first glitch signal before a write operation would have improved the memory system performance. Thus, claims 1-17 of the instant application are not patentably distinct over the patent application because both applications contain substantially the same limitations performing the same function. This is a non-provisional nonstatutory double patenting rejection because the patentably indistinct claims have been patented.
Allowable Subject Matter
9. Claims 1-17 would be allowable once the double patenting rejection and the 35 U.S.C. 101 rejection(s) that set forth in this Office action are overcome. The following is an examiner’s statement of reasons for allowance:
As per claim 1: The prior arts of record taken singly or in combination fail to teach, anticipate, suggest, or render obvious the following limitations. Particularly the prior art Nguyen et al. (U.S. PN: 2022/019919) teaches “A system, comprising: a memory device; and a test device configured to generate a first glitch signal before a write operation of the memory device.” See Fig. 1. The prior arts however are not concerned with and do not teach, suggest, or otherwise render obvious “wherein the test device is further configured to determine, based on write data of the write operation, whether bits of read data outputted in a read operation of the memory device are moved toward a first side to generate a test result indicating a disturbance to the write operation induced by the first glitch signal, wherein when the bits of the read data are moved toward the first side, compared with the write data, at least one mismatched bit between the read data and the write data has a logic high value.” as recited in the independent claim 1. Consequently, claim 1 is/are allowed over the prior arts.
As per claim 8: The prior arts of record taken singly or in combination fail to teach, anticipate, suggest, or render obvious the following limitations. Particularly the prior art Nguyen et al. (U.S. PN: 2022/019919) teaches “a memory device; and a test device that is configured to output a glitch signal and a differential data strobe signal pair to the memory device, wherein the memory device is configured to latch data for a write operation according to the differential data strobe signal pair.” See abstract, paragraphs [0019] and [0021]. The prior arts however are not concerned with and do not teach, suggest, or otherwise render obvious “wherein the test device is further configured to compare write data corresponding to the write operation and read data outputted in a read operation of the memory device to determine whether the memory device is disturbed by the glitch signal, wherein when bits of the read data are moved toward a first side, compared with the write data, at least one mismatched bit between the read data and the write data has a logic high value.” as recited in the independent claim 8. Consequently, claim 8 is/are allowed over the prior arts.
As per claim 13: The prior arts of record taken singly or in combination fail to teach, anticipate, suggest, or render obvious the following limitations. Particularly the prior art Nguyen et al. (U.S. PN: 2022/019919) teaches “generating a write data signal, a glitch signal and a control signal to a memory device; latching data from the write data signal for a write operation in response to at least one of the glitch signal and the control signal; performing a read operation to generate a read data signal after the write operation.” See abstract, paragraphs [0019 and [0021]. The prior arts however are not concerned with and do not teach, suggest, or otherwise render obvious “determining, based on write data signal, whether bits of the read data signal are moved toward a first side to generate a test result indicating a disturbance to the write operation induced by the glitch signal, wherein when the bits of the read data signal are moved toward a first side, compared with the write data signal, at least one mismatched bit between the read data signal and the write data signal has a logic high value.” as recited in the independent claim 13. Consequently, claim 13 is/are allowed over the prior arts. Dependent claims 2-7, 9-12, and 14-17 are depend from allowable independent claims 1 8, and 13 respectively and inherently include limitations therein and therefore are allowed as well. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Examiner Notes
10. When amending the claims, applicants are respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Prior Art
11. The prior art of record, considered pertinent to the applicant’s disclosure, is listed in the attached PTO-892 form.
Conclusion
12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to OSMAN ALSHACK whose telephone number is (571)272-2069. The examiner can normally be reached on MON-FRI 8:30 AM-5:00 PM EST, also please fax interview request to (571) 273- 2069. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ALBERT DECADY can be reached on 5712723819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/OSMAN M ALSHACK/Examiner, Art Unit 2112
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