DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1, 16, and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,293,783. Although the claims at issue are not identical, they are not patentably distinct from each other because:
Regarding claim 1, claim 1 of Pat. ‘783 discloses a memory device, comprising: a command interface configured to receive read commands and write commands to invoke read and write operations; a memory bank comprising a plurality of memory cells implemented using ferroelectric layers between plate lines and digit lines; and bank control circuitry configured to maintain a plate voltage at a constant voltage throughout an entire read and write phase of the memory bank, wherein a same read and write phase comprises programming of both high and low logic values as a write back to the plurality of memory cells during the read and write phase where the read and write operations are performed after sensing values from the plurality of memory cells, wherein programming both the high and low logic values in the same read and write phase comprises swinging the digit lines above and below the constant voltage during the read and write phase.
Regarding claim 16, claim 14 of Pat. ‘783 discloses a memory device, comprising: a plate line; a ferroelectric layer implementing a memory cell of a memory bank and coupled to the plate line; digit lines coupled to the ferroelectric layer; a sense amplifier coupled to the digit lines and configured to sense and amplify a voltage received at the digit lines from the memory cell; and bank control circuitry configured to maintain a plate voltage of the plate line at a constant voltage throughout an entire read and write phase of the memory bank, wherein the read and write phase comprises programming of both high and low logic values as a write back to the memory bank during the read and write phase where the read and write operations are performed after sensing values from the memory bank, wherein programming both the high and low logic values in the same read and write phase comprises swinging the digit lines above and below the constant voltage during the read and write phase.
Regarding claim 20, claim 19 of Pat. ‘783 discloses a method comprising: sensing a stored value stored in a ferroelectric memory cell of a memory bank of a memory device using a sense amplifier; and maintaining a plate voltage of a plate line of the ferroelectric memory cell at a constant voltage throughout programming of the memory bank to both a logic high value and a logic low value during a same read and write phase where read and write operations are being performed for the memory device, wherein programming both the logic high value and the low logic value in the same read and write phase comprises swinging digit lines of the memory bank above and below the constant voltage during the read and write phase.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Akiyama et al. (US Pub. 2004/0225829) in view of Liu (US Pub. 2018/0366174).
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Regarding claims 1, 7, and 11, Fig. 18A and Fig. 18C of Akiyama discloses a memory device, comprising:
a command interface [NWC, Fig. 5] configured to receive read commands [BRQ, Fig. 5] and write commands [MWE#] to invoke read and write operations;
a memory bank [BANK 0 to BANK 127, Fig. 5] comprising a plurality of memory cells [Fig. 18A, paragraph 0112] implemented using ferroelectric layers between plate lines [PLT, Fig. 18A] and digit lines [BL, Fig. 18A]; and
bank control circuitry [NWC in Fig. 5], wherein a same read and write phase comprises programming of both high and low logic values as a write back to the plurality of memory cells during the read and write phase [during RWT and WR periods of Fig. 18C, opposite data are write back to the memory cell. Therefore, both high and low logic values are written] where the read and write operations [tRC, Fig. 18C] are performed after sensing values [RD, Fig. 18C] from the plurality of memory cells.
Akiyama discloses all claimed limitations, but does not specifically disclose bank control circuit configured to maintain a plate voltage at a constant voltage throughout an entire read and write phase of the memory bank, wherein programming both the high and low logic values in the same read and write phase comprises swinging the digit lines above and below the constant voltage during the read and write phase, wherein the constant voltage is a nominal voltage for ferroelectric-based memory cells. However, Fig. 4, Fig.5, and Fig. 6 of Liu discloses reading [Fig. 5] and writing operations [Fig. 4, Fig. 6A, and Fig. 6B] of a ferroelectric memory device wherein a plate voltage [1/2 Vdd, Fig. 4] wherein, bank control circuit configured to maintain a plate voltage at a constant voltage [1/2 Vdd] throughout an entire read [Fig. 5] and write phase [Fig. 4] of the memory bank, wherein programming both the high and low logic values in the same read and write phase comprises swinging the digit lines [S_BL] above and below the constant voltage [swing from -1/2 Vdd to 3/2 Vdd] during the read and write phase, and wherein the constant voltage [1/2 Vdd] is a nominal voltage for ferroelectric-based memory cells.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Liu’s ferroelectric memory having constant voltage for plate lines to Akiyama’s ferroelectric memory such that Akiyama memory operates in a manner according to Liu’s teachings for the purpose of protecting the ferroelectric memory from negative impact by operational voltages [paragraph 0105].
Regarding claims 2 and 17, Fig. 18C of Akiyama discloses wherein the read [RWT] and write [WR] phase comprises a steady wordline voltage [voltage on WL] throughout the read and write phase [voltage on WL are steady during RWT and WR periods].
Regarding claims 3 and 18, Akiyama discloses the wordline voltage is higher than the plate voltage [voltage on PLT], but does not specifically disclose wherein the wordline voltage is three times the constant voltage. It would have been obvious to one having ordinary skill in the art at the time of the invention was made to have the wordline voltage three times the constant voltage (voltage on plate line), since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 4, Fig. 11 of Akiyama discloses wherein the memory bank [BANK 0 to BANK 127] comprises: a plurality of plate lines [PLT] each corresponding to two memory cells [Fig. 18A shows 1 memory cell, but more cells in a bank is inherent], and a plurality of digit lines [BL] each corresponding to a respective memory cell.
Regarding claim 5, Fig. 18C of Akiyama discloses wherein each bit of data to be stored in the memory bank is stored as complementary data in two different memory cells [each cell has bet line [BL] and complement bit line [/BL] in two different memory cells.
Regarding claim 6, Fig. 18A of Akiyama discloses wherein each bit of data to be stored in the memory bank is stored in a single memory cell [MC].
Regarding claims 8-10 and 19, Akiyama in view of Liu the constant voltage is ½ Vdd, maximum voltage for digit line is 3/2 Vdd, and minimum voltage for digit line is -1/2 Vdd, but does not specifically disclose wherein the constant voltage is 1.5V, the maximum voltage for the digit lines is 3.0V, and the minimum voltage for the digit line is 0V. It would have been obvious to one having ordinary skill in the art at the time of the invention was made to have constant voltage is 1.5V, the maximum voltage for the digit lines is 3.0V, and the minimum voltage for the digit line is 0V, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 12, Fig. 5 of Akiyama wherein the bank control circuitry is configured to: receive a write command [MWE#] from the command interface [NWC] during the read and write phase; and program a corresponding memory cell of the plurality of memory cells with a value from the write command [MWE#] during the read and write phase [Fig. 18C].
Regarding claim 13, Fig. 18C discloses wherein the read [RWT] and write [WR] phase follows a tRCD phase that has a defined duration to open a cell, wherein a wordline voltage and the plate voltage increase until the read and write phase [voltage on WL and PLT increase during RD period] where the wordline voltage and the constant voltage remain constant throughout the read and write phase [voltage on WL and PLT are constants during RWT and WR].
Regarding claim 14, Fig. 18C of Akiyama discloses wherein a tRP phase occurs after the read and write phase [during PCH], the tRP phase has a defined duration to close a page of memory, and no programming of high or low logic values is performed during the tRP phase [no program during PCH].
Regarding claim 15, Fig. 18C or Akiyama discloses wherein the voltage of the wordline [WL] and the voltage of the plate line [PLT] decrease to idle values during the tRP phase [voltage on WL and PLT are decreased during PCH].
Regarding claims 16 and 20, Fig. 6 and Fig. 18A of Akiyama discloses a memory device, comprising:
a plate line [PLT, Fig. 18A];
a ferroelectric layer [CO] implementing a memory cell of a memory bank and coupled to the plate line;
digit lines [BL] coupled to the ferroelectric layer [CO];
a sense amplifier [SA & IOBUS, Fig. 6] coupled to the digit lines [BL] and configured to sense [inherent for sense amplifier, paragraph 0048] and amplify a voltage received at the digit lines from the memory cell; and
bank control circuitry [NWC in Fig. 5], wherein a same read and write phase comprises programming of both high and low logic values as a write back to the plurality of memory cells during the read and write phase [during RWT and WR periods of Fig. 18C, opposite data are write back to the memory cell. Therefore, both high and low logic values are written] where the read and write operations [tRC, Fig. 18C] are performed after sensing values [RD, Fig. 18C] from the plurality of memory cells.
Akiyama discloses all claimed limitations, but does not specifically disclose bank control circuit configured to maintain a plate voltage at a constant voltage throughout an entire read and write phase of the memory bank, wherein programming both the high and low logic values in the same read and write phase comprises swinging the digit lines above and below the constant voltage during the read and write phase, wherein the constant voltage is a nominal voltage for ferroelectric-based memory cells. However, Fig. 4, Fig.5, and Fig. 6 of Liu discloses reading [Fig. 5] and writing operations [Fig. 4, Fig. 6A, and Fig. 6B] of a ferroelectric memory device wherein a plate voltage [1/2 Vdd, Fig. 4] wherein, bank control circuit configured to maintain a plate voltage at a constant voltage [1/2 Vdd] throughout an entire read [Fig. 5] and write phase [Fig. 4] of the memory bank, wherein programming both the high and low logic values in the same read and write phase comprises swinging the digit lines [S_BL] above and below the constant voltage [swing from -1/2 Vdd to 3/2 Vdd] during the read and write phase, and wherein the constant voltage [1/2 Vdd] is a nominal voltage for ferroelectric-based memory cells.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Liu’s ferroelectric memory having constant voltage for plate lines to Akiyama’s ferroelectric memory such that Akiyama memory operates in a manner according to Liu’s teachings for the purpose of protecting the ferroelectric memory from negative impact by operational voltages [paragraph 0105].
Conclusion
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/ANTHAN TRAN/Primary Examiner, Art Unit 2825
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