DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6, 10, 14-17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Shi et al (Publication number: US 2023/0007898) in view of Yanagita et al (Publication number: US 2018/0308883).
Consider Claim 1, Shi et al shows a display device (see figures 2 and 4), comprising:
(a) A substrate (see figure 2); (Read as element 206).
(b) A first pixel on the substrate and not surrounded by a light blocking layer; a second pixel on the substrate and surrounded by the light blocking layer (see figure 2; paragraphs 14, 28 and 29); (The first pixel is read as element 204a; and the second pixel is read as element 203a).
(c) A data line connected to the first pixel and the second pixel; a first gate line connected to the first pixel; a second gate line connected to the second pixel (see figure 1; and paragraphs 26-27); (Imaging system 100 includes pixel array 102 coupled to control circuitry 108 and readout circuitry 104, which is coupled to function logic 106. Control circuitry 108 and readout circuitry 104 are in addition coupled to state register 112).
(d) In a first mode, the a first voltage has a voltage of a magnitude capable of turning on a first transistor of the first pixel, in a second mode, the first voltage has a voltage of a magnitude capable of turning off the first transistor of the first pixel, and in the first mode and the second mode, a second voltage has a voltage of a magnitude capable of turning on the first transistor of the second pixel (see paragraphs 26-28); (The control circuitry 108 may generate a shutter signal for controlling image acquisition. In one example, the shutter signal is a global shutter signal for simultaneously enabling all pixels within pixel array 102 to simultaneously capture their respective image data during a single acquisition window. In another example, the shutter signal is a rolling shutter signal such that each row, column, or group of pixels is sequentially enabled during consecutive acquisition windows).
However, Shi et al does not specifically show a first initialization voltage line connected to the first pixel, and configured to transmit a first initialization voltage; and a second initialization voltage line connected to the second pixel, and configured to transmit a second initialization voltage.
In the same field of endeavor, Yanagita et al shows a first initialization voltage line connected to the first pixel, and configured to transmit a first initialization voltage; and a second initialization voltage line connected to the second pixel, and configured to transmit a second initialization voltage (see figures1 and 2; and paragraphs 75-81); (The unit pixel 100 is wired with a plurality of drive lines as the pixel drive lines 16 illustrated in FIG. 1, for example pixel row by pixel row. Then, various drive signals TGL, TGS, FCG, RST, and SEL are supplied via the drive lines from the vertical drive unit 12 illustrated in FIG. 1).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the pixel unit (figure 2) of Yanagita et al into the teachings of Shi et al in order to activate pixels of different sensitivities (see Yanagita et al; paragraphs 75-81).
Consider Claim 20, Shi et al shows an electronic device (see figures 2 and 4), comprising:
(a) A substrate (see figure 2); (Read as element 206).
(b) A first pixel on the substrate and not surrounded by a light blocking layer; a second pixel on the substrate and surrounded by the light blocking layer (see figure 2; paragraphs 14, 28 and 29); (The first pixel is read as element 204a; and the second pixel is read as element 203a).
(c) A data line connected to the first pixel and the second pixel; a first gate line connected to the first pixel; a second gate line connected to the second pixel (see figure 1; and paragraphs 26-27); (Imaging system 100 includes pixel array 102 coupled to control circuitry 108 and readout circuitry 104, which is coupled to function logic 106. Control circuitry 108 and readout circuitry 104 are in addition coupled to state register 112).
(d) In a first mode, the a first voltage has a voltage of a magnitude capable of turning on a first transistor of the first pixel, in a second mode, the first voltage has a voltage of a magnitude capable of turning off the first transistor of the first pixel, and in the first mode and the second mode, a second voltage has a voltage of a magnitude capable of turning on the first transistor of the second pixel (see paragraphs 26-28); (The control circuitry 108 may generate a shutter signal for controlling image acquisition. In one example, the shutter signal is a global shutter signal for simultaneously enabling all pixels within pixel array 102 to simultaneously capture their respective image data during a single acquisition window. In another example, the shutter signal is a rolling shutter signal such that each row, column, or group of pixels is sequentially enabled during consecutive acquisition windows).
However, Shi et al does not specifically show a first initialization voltage line connected to the first pixel, and configured to transmit a first initialization voltage; and a second initialization voltage line connected to the second pixel, and configured to transmit a second initialization voltage.
In the same field of endeavor, Yanagita et al shows a first initialization voltage line connected to the first pixel, and configured to transmit a first initialization voltage; and a second initialization voltage line connected to the second pixel, and configured to transmit a second initialization voltage (see figures1 and 2; and paragraphs 75-81); (The unit pixel 100 is wired with a plurality of drive lines as the pixel drive lines 16 illustrated in FIG. 1, for example pixel row by pixel row. Then, various drive signals TGL, TGS, FCG, RST, and SEL are supplied via the drive lines from the vertical drive unit 12 illustrated in FIG. 1).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the pixel unit (figure 2) of Yanagita et al into the teachings of Shi et al in order to activate pixels of different sensitivities (see Yanagita et al; paragraphs 75-81).
Consider Claim 6, Shi et al in view of Yanagita et al do not specifically show that each of the first transistor of the first pixel and a second transistor of the second pixel is a P-type transistor. However, the USPTO takes official notice that it is well known and expected in the art that each of the first transistor of the first pixel and a second transistor of the second pixel is a P-type transistor in order to achieve simplified fabrication.
Consider Claim 10, Yanagita et al shows that each of the first transistor of the first pixel and the first transistor of the second pixel is an N-type transistor (see paragraph 77).
Consider Claim 14, Yanagita et al shows that the first pixel further includes: a light emitting element connected to the first transistor of the first pixel; and a second transistor connected to a gate electrode of the first transistor of the first pixel and the first initialization voltage line (see figures1 and 2; and paragraphs 75-81); (The unit pixel 100 is wired with a plurality of drive lines as the pixel drive lines 16 illustrated in FIG. 1, for example pixel row by pixel row. Then, various drive signals TGL, TGS, FCG, RST, and SEL are supplied via the drive lines from the vertical drive unit 12 illustrated in FIG. 1).
Consider Claim 15, Yanagita et al shows that the second pixel further includes: a light emitting element connected to the first transistor of the second pixel; and a second transistor connected to a gate electrode of the first transistor of the second pixel and the second initialization voltage line (see figures1 and 2; and paragraphs 75-81); (The unit pixel 100 is wired with a plurality of drive lines as the pixel drive lines 16 illustrated in FIG. 1, for example pixel row by pixel row. Then, various drive signals TGL, TGS, FCG, RST, and SEL are supplied via the drive lines from the vertical drive unit 12 illustrated in FIG. 1).
Consider Claim 16, Shi et al shows that in the first mode, a first data signal corresponding to the first pixel is applied to the data line for a first period, and in the first mode, a second data signal corresponding to the second pixel is applied to the data line for a second period (see paragraphs 101-106).
Consider Claim 17, Shi et al shows that in the second mode, a data signal corresponding to the second pixel is applied to the data line (see figure 1; and paragraphs 26-27); (Imaging system 100 includes pixel array 102 coupled to control circuitry 108 and readout circuitry 104, which is coupled to function logic 106. Control circuitry 108 and readout circuitry 104 are in addition coupled to state register 112).
Consider Claim 19, Shi et al shows that in the first mode, the first pixel and the second pixel are configured to be turned on, respectively, wherein, in the second mode, the first pixel is turned off and the second pixel is configured to be turned on (see paragraphs 26-28); (The control circuitry 108 may generate a shutter signal for controlling image acquisition. In one example, the shutter signal is a global shutter signal for simultaneously enabling all pixels within pixel array 102 to simultaneously capture their respective image data during a single acquisition window. In another example, the shutter signal is a rolling shutter signal such that each row, column, or group of pixels is sequentially enabled during consecutive acquisition windows).
Claims 2-5, 7-9, and 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Shi et al (Publication number: US 2023/0007898) in view of Yanagita et al (Publication number: US 2018/0308883) in view of Yamauchi (Publication number: US 2013/0147783).
Consider Claim 2, Shi et al in view of Yanagita et al do not specifically show that the second initialization voltage has a same magnitude as that of the first initialization voltage in the first mode.
In related art, Yamauchi et al shows that the second initialization voltage has a same magnitude as that of the first initialization voltage in the first mode (see figure 13; and paragraph 160); (See the first initialization operation shown in figure 13).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the initialization signals shown in Yamauchi et al into the teachings of Shi et al and Yanagita et al in order to realize a constant display (see Yamauchi et al; paragraphs 6-8).
Consider Claim 3, Yamauchi et al shows that the second initialization voltage has a same polarity and magnitude as those of the first initialization voltage in the first mode (see paragraph 160; and figure 13).
Consider Claim 4, Shi et al in view of Yanagita et al do not specifically show that the second initialization voltage has a magnitude different from that of the first initialization voltage in the second mode.
In related art, Yamauchi et al shows that the second initialization voltage has a magnitude different from that of the first initialization voltage in the second mode (see figure 12; and paragraph 160); (See the first and second initialization operations shown in figure 12).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the initialization signals shown in Yamauchi et al into the teachings of Shi et al and Yanagita et al in order to reduce fluctuation produced in a voltage (see Yamauchi et al; paragraphs 4-8).
Consider Claim 5, Yamauchi et al shows that the second initialization voltage has an opposite polarity and a different magnitude from the first initialization voltage in the second mode (see paragraph 160; and figure 12).
Consider Claims 7-9, Shi et al in view of Yanagita et al do not specifically show that the first initialization voltage is a voltage of a negative polarity in the first mode, wherein the first initialization voltage is a voltage of a positive polarity in the second mode, wherein the second initialization voltage is a voltage of a negative polarity in the first mode and the second mode.
In related art, Yamauchi et al shows that the first initialization voltage is a voltage of a negative polarity in the first mode, wherein the first initialization voltage is a voltage of a positive polarity in the second mode, wherein the second initialization voltage is a voltage of a negative polarity in the first mode and the second mode (see figure 12; and paragraph 160); (See the first and second initialization operations shown in figure 12).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the initialization signals shown in Yamauchi et al into the teachings of Shi et al and Yanagita et al in order to reduce fluctuation produced in a voltage (see Yamauchi et al; paragraphs 4-8).
Consider Claims 11-13, Shi et al in view of Yanagita et al do not specifically show that the first initialization voltage is a voltage of a positive polarity in the first mode, wherein the first initialization voltage is a voltage of a negative polarity in the second mode, wherein the second initialization voltage is a voltage of a positive polarity in the first mode and the second mode.
In related art, Yamauchi et al shows that the first initialization voltage is a voltage of a positive polarity in the first mode, wherein the first initialization voltage is a voltage of a negative polarity in the second mode, wherein the second initialization voltage is a voltage of a positive polarity in the first mode and the second mode (see figure 12; and paragraph 160); (See the first and second initialization operations shown in figure 12).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the initialization signals shown in Yamauchi et al into the teachings of Shi et al and Yanagita et al in order to reduce fluctuation produced in a voltage (see Yamauchi et al; paragraphs 4-8).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Shi et al (Publication number: US 2023/0007898) in view of Yanagita et al (Publication number: US 2018/0308883) in view of Ma et al (Publication number: US 2021/0159286).
Consider Claim 18, Shi et al in view of Yanagita et al do not specifically show that the first pixel is included in any one of an odd-numbered rendering group and an even-numbered rendering group, and the second pixel is included in the other one of the odd-numbered rendering group and the even-numbered rendering group.
In related art, Ma et al shows that the first pixel is included in any one of an odd-numbered rendering group and an even-numbered rendering group, and the second pixel is included in the other one of the odd-numbered rendering group and the even-numbered rendering group (see paragraphs 49-50).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the teachings of Ma et al into the teaching of Shi et al and Yanagita et al in order to implement full screen display (see Ma et al; paragraphs 3-5).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL A FARAGALLA whose telephone number is (571)270-1107. The examiner can normally be reached Mon-Fri 8:00-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached at 571-270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL A FARAGALLA/Primary Examiner, Art Unit 2624 05/12/2026
Prosecution Insights