DETAILED ACTION
The action is responsive to the following communications: the Application filed April 10, 2025.
Claims 1-20 are pending. Claims 1, 9 and 14 are independent.
Notice of Pre-AIA or AIA Status
The present application is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention, MANAGING PROGRAM OPERATIONS IN MEMORY SYSTEMS, is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Drawings
The drawings are objected to because:
Figures 1-5 should be designated by a legend such as –Prior Art—because only that which is old is illustrated. See MPEP 608.02(g).
Applicant is reminded of helpful scenario 7, described in MPEP 2004, and encouraged to carefully review instant application’s Specification and Figures to make sure care is taken to see that prior art or other information cited in the Specification and Figures or in an information disclosure statement is properly described and that the information is not incorrectly or incompletely characterized. MPEP 2004, Scenario 7; see also MPEP 2010.
Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 9-12, 14-17 and 20 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2022/0406398).
Regarding independent claims 1, 9 and 14, Yang et al. teach a memory system, comprising:
a memory device (e.g., FIG. 1A); and
a memory controller (FIG. 1A: 110) coupled to the memory device, wherein the memory controller is configured to:
instruct the memory device to write first data in a first single-level cell (SLC) mode using a first program pulse (e.g., FIG. 21: 2100-2103, a foggy program … concurrently programs and the pages of SLC data …; see also FIG. 22A, after a foggy program pass of a program operation (para. 0048)); and
in response to detecting that the memory system is disconnected from an external power source (FIG. 21: 2104), instruct the memory device to write second data in a second SLC mode using a second program pulse, wherein the second program pulse is different from the first program pulse (FIG. 21: 2105-2108, … decodes the pages of SLC data … programs …); see also FIG. 22B, after a fine program pass of a program operation, following the foggy program (para. 0049)).
Yang et al. do not explicitly disclose an external power source.
However, an external power source, such as Yang’s FIG. 3B, is an inherent characteristic of the memory devices.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize an external power source in memory because these conventional technologies are well established in the art of the memory devices.
Regarding claims 2, 10 and 15, Yang et al. teach the limitations of claims 1, 9 and 14, respectively.
Yang et al. further teach the memory device is configured to: write the first data in the first SLC mode by applying the first program pulse; and write the second data in the second SLC mode by applying the second program pulse, wherein a voltage of the second program pulse is lower than a voltage of the first program pulse (see e.g., FIGS. 22A-22B, integrated pulses having higher voltage, further “fine” is lower than “foggy” is an inherent characteristics).
Regarding claims 3, 11 and 16, Yang et al. teach the limitations of claims 1, 9 and 14, respectively.
Yang et al. further teach the memory device is configured to: write the first data in the first SLC mode by applying the first program pulse; and write the second data in the second SLC mode by applying the second program pulse, wherein a duration of the second program pulse is shorter than a duration of the first program pulse (see e.g., FIGS. 22A-22B, further “fine” is shorter than “foggy” is an inherent characteristics).
Regarding claims 4 and 12, Yang et al. teach the limitations of claims 1, 9 and 14, respectively.
Yang et al. further teach the memory controller is configured to instruct the memory device to write the second data in the second SLC mode by: sending configuration information that indicates the second SLC mode; and sending a write command that instructs the memory device to write the second data (e.g., FIG. 21 and accompanying disclosure).
Regarding claim 17, Yang et al. teach the limitations of claim 14.
Yang et al. do not explicitly disclose the memory device receives the configuration information when an external power source of the memory device is disconnected.
However, the claimed limitation is a well-known technology in power management system for a memory device.
For support, of the above asserted facts, see for example, Wang et al. (US 11,404,906), e.g., col. 12, lines 10-30: … disconnected the failed power … The system also sends a signal to inform the Soc controller of the internal power failure event. … . and provide an effective internal power loss protection in SSDs.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize power management in the memory device because these conventional technology are well established in the art of the memory devices.
Regarding claim 20, Yang et al. teach the limitations of claim 14.
Yang et al. further teach the peripheral circuit is configured to: apply the second program pulse to a word line to program memory cells coupled to the word line from an erased state to a programmed state (see e.g., FIGS. 7A-9, and accompanying disclosure, e.g., para. 0161-0163: … The memory cells are initially in the erased state …; further programming memory from erase state is an inherent characteristic in the flash memory device).
Claims 5-6 and 13 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2022/0406398) in view of e.g., Oh et al. (US 2024/0202081).
Regarding claim 5, Yang et al. teach the limitations of claim 1.
Yang et al.’ single-level data for power loss protection (see title) does not explicitly disclose comprising a power loss protection (PLP) circuit configured to provide power for the memory system when the memory system is disconnected from the external power source.
However, PLP circuit for providing power system to memory system is a well-known technology for a type of memory (e.g., flash memory) for its purpose.
For support, of the above asserted facts, see for example, Oh et al., e.g., FIG. 10, power loss protection circuit, and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Oh et al. to the teaching of Yang et al. such that a memory, as taught by Yang et al., utilizes a PLP circuit, as taught by Oh et al., for the purpose of controlling power supply, and further these conventional technology are well established in the art of the memory devices.
Regarding claim 6, Yang et al. and Oh et al., as combined, teach the limitations of claim 5.
Oh et al. further teach wherein the PLP circuit comprises a capacitor, wherein the PLP circuit is configured to: charge the capacitor when the memory system is connected to the external power source; and discharge the capacitor to provide power for the memory system when the memory system is disconnected from the external power source (see e.g., FIG. 10: Charging Capacitor and Capacitor Discharge, and accompanying disclosure).
Regarding claim 13, Yang et al. teach the limitations of claim 9.
Yang et al. are silent with respect to discharging a power loss protection circuit to provide power for the memory system when the memory system is disconnected from the external power source.
However, PLP circuit for providing power system to memory system is a well-known technology for a type of memory (e.g., flash memory) for its purpose.
For support, of the above asserted facts, see for example, Oh et al., e.g., FIG. 10, power loss protection circuit, and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Oh et al. to the teaching of Yang et al. such that a memory, as taught by Yang et al., utilizes a PLP circuit, as taught by Oh et al., for the purpose of controlling power supply, and further these conventional technology are well established in the art of the memory devices.
Claims 7-8 and 18-19 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2022/0406398) in view of Mizukoshi et al. (US 2022/0392555).
Regarding claims 7-8 and 18-19, Yang et al. teach the limitations of claims 1 and 14, respectively.
Yang et al. do not explicitly disclose the memory device comprises memory cells programmable in the first SLC mode, the second SLC mode and a third storage mode, wherein memory cells programmable in the third storage mode have a higher storage density than memory cells programmable in the first SLC mode and the second SLC mode; wherein the third storage mode comprises a triple-level cell (TLC) storage mode or a quad-level cell (QLC) storage mode (see e.g., FIGS. 15-16 and accompanying disclosure, i.e., after power down a third storage mode QLC data).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Mizukoshi et al. to the teaching of Yang et al. such that a memory, as taught by Yang et al., utilizes a programming after power down, as taught by Mizukoshi et al., for the purpose of controlling power supply for a memory device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached on M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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/SUNG IL CHO/Primary Examiner, Art Unit 2825
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