DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
2. The information disclosure statement (IDS) submitted on 04/11/25 has been considered by the examiner.
Claim Rejections - 35 USC § 112
3. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 12 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
On the first line of claim 12, the recitation of a fourth power clamp lacks antecedent basis, the reason being that neither claim 1 nor claim 12 recites any first through third power clamps, which are necessary for purposes of proper antecedent basis, before reciting a fourth power clamp.
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5, 12, 13, 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Bui (USP 7,589,584) in view of any one of Davis et al (USPAP 2024/0372360), Chen et al (USPAP 2003/0227726) and Ker et al (USP 6,002,568).
As to claim 1, Bui discloses, in figure 2,
an electronic device comprising:
a post driver voltage rail (post driver voltage rail 42) having an overdrive voltage (overdrive voltage 3.3V) greater than an operating voltage (operating voltage 1.8-3.3V) of an operating voltage rail (operating voltage rail 38); and
a low-side logic-high voltage rail (low-side logic-high voltage rail 40) coupled to a supply voltage rail (supply voltage rail 44).
Not disclosed by Bui is the claimed first power-to-power clamp circuit coupled to the low-side logic-high voltage rail and the post driver voltage rail. Such would have been obvious, however, to one of ordinary skill in the art, the reason being that it was old and well-known in the art before the effective filing date of applicant’s invention to couple a power-to-power clamp circuit between the power supply rails of an integrated circuit, three examples of this well-known concept being disclosed by Davis et al (note power-to-power clamp circuit 255 shown in figure 2), Chen et al (note power-to-power clamp circuit 8 shown in figure 1), and Ker et al (note the power-to-power clamp circuit including diodes 20a through 20d and 22a shown in figure 4), the motivation for adding such a power-to-power clamp circuit between power supply rails 40 and 42 in figure 2 of Bui is to provide the well-known advantages associated with using such a power-to-power clamp circuit, i.e., providing protection to sensitive internal IC components from damage by limiting the voltage difference between such power supply rails during a high-voltage ESD event, note that such a power-to-power clamp circuit, when added to Bui’s figure 2 circuitry, will inherently be configured to receive electrostatic discharge (ESD) when the above-noted obvious power-to-power clamp circuit is added to the Bui figure 2 electronic device, i.e., it will receive ESD current between post driver voltage rail 42 and low-side logic-high voltage rail 40.
As to claim 2, it also would have been obvious to use the claimed forward diode string to implement the above-noted power-to-power clamp circuit, the reason being that it was old and well-known in the art before the effective filing date of applicant’s invention that a power-to-power clamp circuit typically includes a forward diode string for use in implementing a power-to-power clamp circuit, one example of this well-known concept being disclosed by and the motivation for using such a teaching by Tsai et al, note figures 1A and 1B of this reference, and note further that the motivation for using such a forward diode string in the obvious power-to-power clamp circuit in Bui’s figure 2 is simply to use any well-known circuit arrangement for implementing the power-to-power clamp circuit.
As to claim 3, it also would have been obvious to use the claimed resistor and capacitor connected in series and a plurality of transistors to implement the above-noted power-to-power clamp circuit, the reason being that it was old and well-known in the art before the effective filing date of applicant's invention that a power-to-power clamp circuit typically includes a resistor and capacitor connected in series and a plurality of transistors, four examples of this well-known concept being disclosed by Lai et al (note the power-to-power clamp circuit shown at the right hand side of figure 3), Altolaguirre et al (note the power-to-power clamp circuit 200' shown in figure 2B), Suzuki (note the power-to-power clamp circuit shown in figure 13A), and Peng et al (note the power-to-power clamp circuit 20 shown in figure 4). The motivation for using the circuitry disclosed by Lai et al, Altolaguirre et al, Suzuki or Peng et al to implement the above-noted obvious power-to-power clamp circuit in Bui's figure 2 is again simply to use any well-known circuitry for forming a power-to-power clamp circuit.
As to claim 4, the claimed first and second power clamp circuits, although not disclosed by Bui, also would have been obvious to one of ordinary skill in the art, the reason being that it was also old and well-known in the art before the effective filing date of applicant's invention to couple first and second power clamp circuits, respectively, across a first pair of high and low power supply rails and a second pair of high and low power supply rails, i.e., a first power clamp connected between rails 42 and 44 in figure 2 of Bui and a second power clamp connected between rails 40 and 44 in figure 2 of Bui, three examples of this well-known concept being disclosed by Davis et al (note first and second power clamps 268 in figure 2), Chen et al (note 1st and second power clamps 2 and 20 in figure 1), and Ker et al (note the first power clamp to the left of Circuit I and the second power clamp to the right of Circuit II). The motivation for adding such first and second power clamp circuits in the figure 2 electronic device of Bui is to prevent the power supply rails 40 and 42 from receiving damaging ESD spikes which could be passed from one rail to the other.
As to claim 5, it also would have been obvious to one of ordinary skill in the art to include a first diode string, the reason being that such a diode string having an anode coupled to the lower voltage rail and a cathode coupled to the higher voltage rail, i.e., coupled between voltage rails 40 and 42 in figure 2 of Bui, was also old and well-known in the art, note diode 22a shown in figure 4 of Ker et al, diode D1 shown in figure 3 of Chen et al '970, and the two series connected bottom diodes within power to power clamp circuit 14 shown in figure 1 of Huang et al '767 as several examples of this well-known concept. The motivation for using such a diode string in the above-noted obvious power-to-power clamp in Bui's figure 2 is to provide the well-known advantages of using such a diode string connected in parallel with the power clamp diodes between the two different high-voltage power rails.
As to claim 12, the use of a further power clamp between voltage rails 38 and 44, although not disclosed by Bui, also would have been obvious to one of ordinary skill in the art, the reason being that it was old and well-known in the art to include such a power clamp circuit for protecting against ESD events occurring across the supply voltage rails of an integrated circuit, of which fact official notice is taken by the examiner.
As to claim 13, Bui discloses, in figure 2,
an electrostatic discharge (ESD) protection circuit (just preamble language but note that when figure 2 of Bui is modified as noted above, the resulting figure 2 circuit will be an ESD protection circuit) comprising:
a first power clamp circuit coupled to a supply voltage rail and a post driver voltage rail (obvious, as noted above in the rejection of claim 4); and
a first power-to-power clamp circuit coupled to a low-side logic-high voltage rail and the post driver voltage rail (obvious, as noted above in the rejection of claim 1), the first
power-to-power clamp circuit configured to receive ESD current between the post driver voltage rail and the low-side logic-high voltage rail (such will be the inherent result when a power-to-power clamp circuit is connected between post driver voltage rail 42 and low-side logic-high voltage rail 40 in figure 2 of Bui).
As to claim 15, the limitations of this claim would have been obvious for the reason noted above in the rejection of claim 2.
As to claim 16, the limitations of this claim would have been obvious for the reason noted above in the rejection of claim 3.
Double Patenting
5. Claims 1-20 are rejected on the ground of non-statutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,301,219. Although the claims at issue are not identical, they are not patentably distinct from each other because all of the limitations of claims 1-20 of the present application are fully anticipated by what is recited in 1-20 of applicant's prior patent.
As to claim 1 of the present application, note that the preamble recited on the first line is anticipated by what is recited on the first line of claim 1 of the '219 patent; the limitations recited on lines 2-3 of claim 1 of the present application are fully anticipated by what is recited on lines 8-10 of claim 1 of the '219 patent; the limitation recited on line 4 of claim 1 of the present application is fully anticipated by what is recited on lines 2-3 and 14-15 of claim 1 of the ''19 patent; and the limitations recited on lines 5-8 of claim 1 of the present application are fully anticipated by what is recited on lines 16-22 of claim 1 of the '219 patent.
As to claim 2 of the present application, the limitations of this claim are fully anticipated by what is recited in claim 2 of the '219 patent.
As to claim 3 of the present application, the limitations of this claim are fully anticipated by what is recited in claim 3 of the '219 patent.
As to claim 4 of the present application, the limitations of this claim are fully anticipated by what is recited on lines 11-13 of claim 1 of the '219 patent, together with what is recited in claim 4 of the '219 patent.
As to claim 5 of the present application, the limitations of this claim are fully anticipated by what is recited in claim 5 of the '219 patent.
As to claim 6 of the present application, the limitations of this claim are fully anticipated by what is recited on lines 2-7 of claim 1 of the '219 patent, together with what is recited in claim 6 of the '219 patent.
As to claims 7-12 of the present application, the limitations of these claims are fully anticipated by what is recited in claims 7-12, respectively, of the '219 patent.
As to claims 13-20 of the present application, the limitations of these claims are fully anticipated by what is recited in claims 13-20, respectively, of the '219 patent.
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a non-statutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Allowable Subject Matter
6. Claims 19 and 20 would be allowable upon the filing of the above-noted terminal disclaimer.
Claims 6-11, 14, 17 and 18 would be allowable upon the filing of the above-noted terminal disclaimer and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: none of the prior art of record is seen to disclose or suggest the electronic device recited in claim 6, specifically the limitations of a high-side logic-low voltage rail and a second power-to-power clamp circuit coupled between the high-side logic-low voltage rail post driver voltage rail. Claims 7-11 are allowable in view of their dependencies on allowable claim 6. Claim 14 is allowable because none of the prior art of record is seen to disclose or suggest the claimed third power clamp circuit coupled between a supply voltage rail and a high-side logic-low voltage rail. Claim 17 is allowable because none of the prior art of record is seen to disclose or suggest the claimed second power-to-power clamp circuit coupled between a high-side logic-low voltage rail and a post driver voltage rail. Claim 18 is allowable because none of the prior art of record is seen to disclose or suggest the claimed second power-to-power clamp circuit coupled between a high-side logic-low voltage rail and a post driver voltage rail. Claim 19 is allowable because none of the prior art of record is seen to disclose or suggest the step of maintaining, with a power-to-power clamp, a second voltage difference between a post driver voltage rail and a high-side logic-low voltage rail. Claim 20 is allowable in view of its dependency on allowable claim 19.
Prior Art Not Relied Upon
7. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Figure 2 of Lacey et al discloses an electronic circuit similar to that of figure 2 of Bui, i.e., an electronic circuit including a post driver voltage rail VCCIO, an operating voltage rail VCCIN, a low-side logic-high voltage rail VCCINT, and a supply voltage rail VSS, and it would have been obvious to one of ordinary skill in the art, using the same analysis as set forth above in the rejection based on Bui, to include a power-to-power clamp circuit between VCCIO and VCCINT, to include a first power clamp circuit between VCCIO and VSS, and to include a second power clamp circuit between VCCINT and VSS.
Conclusion
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH B WELLS whose telephone number is (571)272-1757. The examiner can normally be reached Monday-Friday, 8:30am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, REGIS J BETSCH, can be reached at (571)270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KENNETH B WELLS/Primary Examiner, Art Unit 2836 June 26, 2026
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