DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 8, 9 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0116559 to Park et al.; in view of US 2008/0024418 to Kim; in view of US 2012/0169695 to Chang et al.
As per claim 1, Park et al. teach a display apparatus comprising:
a display panel (Fig. 1, 110) comprising a pixel (Fig. 1, PX);
a gate driver (Fig. 1, 120) configured to output gate signals (Fig. 1, GW, GC, GI, GB) to the display panel, and comprising:
a data driver (Fig. 1, 130) configured to apply a data voltage (Fig. 1, DS) to the display panel.
Park et al. do not teach a first gate stage group for generating a first gate signals, and comprising a first gate odd stage group on a first side of the display panel, and a first gate even stage group on a second side of the display panel; and a second gate stage group for generating a second gate signals, and comprising a second gate odd stage group on the second side, and a second gate even stage group on the first side.
Kim suggests a first gate stage group (Fig. 3, 410a/420b) for generating a first gate signals of a first type, and comprising a first gate odd stage group on a first side of the display panel (Fig. 3, 410a, paragraph 71), and a first gate even stage group (Fig. 3, 420b, paragraph 71) on a second side of the display panel; and a second gate stage group (Fig. 3, 410b/420a) for generating a second gate signals, and comprising a second gate odd stage group on the second side (Fig. 3, 410b, paragraph 71), and a second gate even stage group on the first side (Fig. 3, 420a, paragraph 71).
It would have been obvious to one of ordinary skill in the art, to modify the device of Park et al., by including a first gate stage group for generating a first gate signals, and comprising a first gate odd stage group on a first side of the display panel, and a first gate even stage group on a second side of the display panel; and a second gate stage group for generating a second gate signals, and comprising a second gate odd stage group on the second side, and a second gate even stage group on the first side, such as taught by Kim, for the purpose of reducing RC delay.
Park and Kim et al. do not teach the second gate signals of a second type that is different from the first type.
Chang et al. teach the second gate signals of a second type that is different from the first type (Fig. 2, at least 3 types of gate signals Ga, Gb and Gc are generated for particular groups of gate lines, each with a different slope).
It would have been obvious to one of ordinary skill in the art, to modify the device of Park and Kim et al., so that the second gate signals are of a second type that is different from the first type, such as taught by Chang et al., for the purpose of improving display uniformity.
As per claim 2, Park, Kim and Chang et al. teach the display apparatus of claim 1, wherein the display panel further comprises an odd pixel-row (Kim, Fig. 3, odd rows) connected to the first gate odd stage group (Fig. 3, 410a) and the second gate odd stage group (Fig. 3, 410b), and an even pixel-row (Kim, Fig. 3, even rows) connected to the first gate even stage group (Fig. 3, 420a) and the second gate even stage group (Fig. 3, 420b).
As per claim 8, Park, Kim and Chang et al. teach the display apparatus of claim 1, wherein the gate driver further comprises a third gate stage group for generating third gate signals on the first side, and a fourth gate stage group for generating fourth gate signals on the second side (Kim, Figs. 3 and 5 are exemplary embodiments suggesting different amount of groups. In other words, Figs. 3 and 5 suggest an arbitrary number of groups, each group on the one side corresponding to a 2 * i + j row, and comprising a corresponding complementary group on the other side).
As per claim 9, Park, Kim and Chang et al. teach the display apparatus of claim 1, wherein the gate driver further comprises: a third gate stage group for generating third gate signals, and comprising a third gate odd stage group on the first side, and a third gate even stage group on the second side; and a fourth gate stage group for generating fourth gate signals, and comprising fourth gate odd stage group on the second side, and a fourth gate even stage group on the first side (Kim, Figs. 3 and 5 are exemplary embodiments suggesting different amount of groups. In other words, Figs. 3 and 5 suggest an arbitrary number of groups, each group on the one side corresponding to a 2 * i + j row, and comprising a corresponding complementary group on the other side).
As per claim 20, Park et al. teach an electronic apparatus comprising:
a display panel (Fig. 1, 110) comprising a pixel (Fig. 1, PX);
a gate driver (Fig. 1, 120) configured to output gate signals (Fig. 1, GW, GC, GI, GB) to the display panel, and comprising:
a data driver (Fig. 1, 130) configured to apply a data voltage (Fig. 1, DS) to the display panel.
Park et al. do not teach a first gate stage group for generating a first gate signals, and comprising a first gate odd stage group on a first side of the display panel, and a first gate even stage group on a second side of the display panel; and a second gate stage group for generating a second gate signals, and comprising a second gate odd stage group on the second side, and a second gate even stage group on the first side.
Kim suggests a first gate stage group for generating a first gate signals of a first type (Fig. 3, 410a/420a), and comprising a first gate odd stage group on a first side of the display panel (Fig. 3, 410a, paragraph 71), and a first gate even stage group (Fig. 3, 420a, paragraph 71) on a second side of the display panel; and a second gate stage group (Fig. 3, 410b/420b) for generating a second gate signals, and comprising a second gate odd stage group on the second side (Fig. 3, 410b, paragraph 71), and a second gate even stage group on the first side (Fig. 3, 420b, paragraph 71).
It would have been obvious to one of ordinary skill in the art, to modify the device of Park et al., by including a first gate stage group for generating a first gate signals, and comprising a first gate odd stage group on a first side of the display panel, and a first gate even stage group on a second side of the display panel; and a second gate stage group for generating a second gate signals, and comprising a second gate odd stage group on the second side, and a second gate even stage group on the first side, such as taught by Kim, for the purpose of reducing RC delay.
Park and Kim et al. do not teach the second gate signals of a second type that is different from the first type.
Chang et al. teach the second gate signals of a second type that is different from the first type (Fig. 2, at least 3 types of gate signals Ga, Gb and Gc are generated for particular groups of gate lines, each with a different slope).
It would have been obvious to one of ordinary skill in the art, to modify the device of Park and Kim et al., so that the second gate signals are of a second type that is different from the first type, such as taught by Chang et al., for the purpose of improving display uniformity.
Claims 3-6 and 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0116559 to Park et al.; further ion view of US 2008/0024418 to Kim; in view of US 2012/0169695 to Chang et al.; in view of US 2022/0284850 to Park et al., from here-on referred to as Park2.
As per claim 3, Park, Kim and Chang et al. teach the display apparatus of claim 1.
Park, Kim and Chang et al. do not teach wherein the first gate stage group comprises a first-first gate stage, a first-second gate stage, a first-third gate stage, and a first-fourth gate stage, and wherein the first-third gate stage is configured to receive a first-first gate carry signal of the first-first gate stage, and the first-fourth gate stage is configured to receive a first-second gate carry signal of the first-second gate stage.
Park2 suggests wherein the first gate stage group comprises a first-first gate stage, a first-second gate stage, a first-third gate stage, and a first-fourth gate stage, and wherein the first-third gate stage (Fig. 11, GWST(2)) is configured to receive a first-first gate carry signal of the first-first gate stage (Fig. 11, GWST(1)), and the first-fourth gate stage (Fig. 11, GWST(4)) is configured to receive a first-second gate carry signal of the first-second gate stage (Fig. 11, GWST(3)).
It would have been obvious to one of ordinary skill in the art, to modify the device of Park, Kim and Chang et al., so that the first gate stage group comprises a first-first gate stage, a first-second gate stage, a first-third gate stage, and a first-fourth gate stage, and wherein the first-third gate stage is configured to receive a first-first gate carry signal of the first-first gate stage, and the first-fourth gate stage is configured to receive a first-second gate carry signal of the first-second gate stage, such as taught by Park2, for the purpose of individually controlling each generated signal.
As per claim 4, Park, Kim, Chang and Park2 teach the display apparatus of claim 3, wherein the second gate stage group comprises a second-first gate stage (Park2, Fig. 11, GWST(1) analogue to the second stage group), a second-second gate stage (Park2, Fig. 11, GWST(3) analogue to the second stage group), a second-third gate stage (Park2, Fig. 11, GWST(2) analogue to the second stage group) and a second-fourth gate stage (Park2, Fig. 11, GWST(4) analogue to the second stage group), and wherein the second-third gate stage (Park2, Fig. 11, GWST(2) analogue to the second stage group) is configured to receive a second-first gate carry signal of the second-first gate stage (Park2, Fig. 11, GWST(1) analogue to the second stage group), and the second-fourth gate stage (Park2, Fig. 11, GWST(4) analogue to the second stage group) is configured to receive a second-second gate carry signal of the second-second gate stage (Park2, Fig. 11, GWST(3) analogue to the second stage group).
As per claim 5, Park, Kim and Chang et al. teach the display apparatus of claim 1, further comprising an emission driver (Park, Fig. 1, 140) configured to output an emission signal (Park, Fig. 1, EM) to the display panel.
Park, Kim and Chang et al. do not necessarily teach an emission stage group for generating the emission signal.
Park 2 suggests an emission stage group for generating the emission signal (Fig. 11, each signal within each driver is generated by a corresponding stage group).
It would have been obvious to one of ordinary skill in the art, to modify the device of Park, Kim and Chang et al., by including an emission stage group for generating the emission signal, such as taught by Park2, for the purpose of individually controlling each generated signal.
Park, Kim, Chang and Park2 teach the emission stage group comprising an emission odd stage group on the first side, and an emission even stage group on the second side (Kim, Figs. 1 and 3, paragraph 71, a driver is split onto odd and even groups provided to each side of the display panel).
As per claim 6, Park, Kim, Chang and Park2 et al. teach the display apparatus of claim 5, wherein the emission stage group comprises a first emission stage (Park2, Fig. 11, GWST(1) analogue to the emission stage group), a second emission stage (Park2, Fig. 11, GWST(3) analogue to the emission stage group), a third emission stage (Park2, Fig. 11, GWST(2) analogue to the emission stage group) configured to receive a first emission carry signal of the first emission stage, and a fourth emission stage (Park2, Fig. 11, GWST(4) analogue to the emission stage group) configured to receive a second emission carry signal of the second emission stage.
As per claim 10, Park, Kim and Chang et al. teach the display apparatus of claim 1.
Park, Kim and Chang et al. do not explicitly teach wherein the gate driver further comprises an integration gate stage group, wherein at least one integration gate stage of the integration gate stage group comprises: an integration-carry-signal-generating block configured to generate an integration gate stage carry signal in response to a previous integration gate stage carry signal; a third-gate-signal-generating block configured to generate a third gate signal in response to the integration gate stage carry signal; and a fourth-gate-signal-generating block configured to generate a fourth gate signal in response to the integration gate stage carry signal.
Park2 suggests wherein the gate driver further comprises an integration gate stage group (Fig. 11, the gate driver comprises a group of signal generating stages), wherein at least one integration gate stage of the integration gate stage group comprises: an integration-carry-signal-generating block configured to generate an integration gate stage carry signal in response to a previous integration gate stage carry signal (Fig. 11, GWST(2) generates a carry signal in response to carry signal from GWST(1)); a third-gate-signal-generating block (Park2, Fig. 11, GWST(2)) configured to generate a third gate signal in response to the integration gate stage carry signal (Park2, Fig. 11, GWST(1)); and a fourth-gate-signal-generating block configured to generate a fourth gate signal in response to the integration gate stage carry signal (Park2, Fig. 11, GWST(4) is at least indirectly generated based on (Park2, Fig. 11, GWST(1)).
It would have been obvious to one of ordinary skill in the art, to modify the device of Park, Kim and Chang et al., so that the gate driver further comprises an integration gate stage group, wherein at least one integration gate stage of the integration gate stage group comprises: an integration-carry-signal-generating block configured to generate an integration gate stage carry signal in response to a previous integration gate stage carry signal; a third-gate-signal-generating block configured to generate a third gate signal in response to the integration gate stage carry signal; and a fourth-gate-signal-generating block configured to generate a fourth gate signal in response to the integration gate stage carry signal, such as taught by Park2, for the purpose of individually controlling each generated signal.
As per claim 11, Park, Kim, Chang and Park2 teach the display apparatus of claim 10, wherein the integration gate stage group is on the first side (Kim, Fig. 3, drivers on each side comprise signal generating stages, such as those in Fig. 11 of Park 2, so as to generate the required driving signals).
As per claim 12, Park, Kim, Chang and Park2 teach the display apparatus of claim 10, wherein the integration gate stage group comprises an integration gate odd stage group on the first side, and an integration gate even stage group on the second side (Kim, Fig. 3, drivers on each side comprise signal generating stages, such as those in Fig. 11 of Park 2, so as to generate the required driving signals).
As per claim 13, Park, Kim, Chang and Park2 teach the display apparatus of claim 12, wherein the integration gate odd stage group comprises a third integration gate stage (Park2, Fig. 11, GWST(1)) and a first integration gate stage (Park2, Fig. 11, GWST(2)) configured to receive the previous integration gate stage carry signal of the third integration gate stage (Park2, Fig. 11, GWST(1)) as the integration gate stage carry signal, and wherein the integration gate even stage group comprises a fourth integration gate stage (Park2, Fig. 11, GWST(3)), and a second integration gate stage (Park2, Fig. 11, GWST(4)) configured to receive the previous integration gate stage carry signal of the fourth integration gate stage as the integration gate stage carry signal (Park2, Fig. 11, in other words, the current claim language seems to read on a current stage generating a carry signal based on another carry signal received from a previous stage).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0116559 to Park et al.; further in view of US 2008/0024418 to Kim; in view of US 2012/0169695 to Chang et al.; in view of US 2008/0191980 to Jeon.
As per claim 7, Park, Kim and Chang et al. teach the display apparatus of claim 1.
Park, Kim and Chang et al. do not teach a left side clock signal line group on the first side, and a right side clock signal line group on the second side.
Jeon suggests a left side clock signal line group on the first side (Fig. 4, CLK2/CLK4), and a right side clock signal line group on the second side (Fig. 4, CLK1/CLK3).
It would have been obvious to one of ordinary skill in the art, to modify the device of Park, Kim and Chang et al., by including a left side clock signal line group on the first side, and a right side clock signal line group on the second side, such as suggested by Jeon, for the purpose of performing signal synchronization.
Claims 14-19 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0116559 to Park et al.; in view of US 20220284850 to Park et al., from here-on referred to as Park2; further in view of US 2008/0024418 to Kim.
As per claim 14, Park et al. teach a display apparatus comprising:
a display panel (Fig. 1, 110) comprising a pixel (Fig. 1, PX);
a gate driver (Fig. 1, 120) configured to output a write gate signal (Fig. 1, GW) and a bias gate signal (Fig. 1, GB) to the display panel, and
an emission driver (Fig. 1, 140) configured to output an emission signal (Fig. 1, EM) to the display panel, and
a data driver (Fig. 1, 130) configured to apply a data voltage (Fig. 1, DS) to the display panel.
Park et al, do not explicitly teach a bias gate stage group for generating the bias gate signal,
and an emission stage group for generating the emission signal.
Park2 teaches a bias gate stage group for generating the bias gate signal, and an emission stage group for generating the emission signal (Figs. 3 and 11, paragraph 106, each of signals GW, GC, GI and EB is generated by its own dedicated stage group within the data driver).
It would have been obvious to one of ordinary skill in the art, to modify the device of Park et al., by including a bias gate stage group for generating the bias gate signal, and an emission stage group for generating the emission signal, such as taught by Park2, for the purpose of individually controlling each generated signal.
Park and Park2 do not teach the bias gate stage group comprising a bias gate odd stage group on a first side of the display panel, and a bias gate even stage group on a second side of the display panel; the emission stage group comprising an emission odd stage group on the second side, and an emission even stage group on the first side.
Kim suggests the bias gate stage group comprising a bias gate odd stage group on a first side of the display panel, and a bias gate even stage group on a second side of the display panel; the emission stage group comprising an emission odd stage group on the second side, and an emission even stage group on the first side (Figs. 1 and 3, paragraph 71, a driver is split onto odd and even groups provided to each side of the display panel).
It would have been obvious to one of ordinary skill in the art, to modify the device of Park and Park2 et al., so that the bias gate stage group comprises a bias gate odd stage group on a first side of the display panel, and a bias gate even stage group on a second side of the display panel; and the emission stage group comprising an emission odd stage group on the second side, and an emission even stage group on the first side, such as taught by Kim, for the purpose of reducing RC delay.
As per claim 15, Park, Park2 and Kim teach the display apparatus of claim 14, wherein the display panel comprises an odd pixel-row connected to the bias gate odd stage group and the emission odd stage group, and an even pixel-row connected to the bias gate even stage group and the emission even stage group (Park, Fig. 4, pixels in each row comprise bias gate signals GB and emission signals EM. Furthermore, Kim discloses (Fig. 3) wherein drivers supplying scan signals are divided into odd and even sub-drivers. Park2 discloses (Fig. 11) wherein each signal is generated by a corresponding stage group).
As per claim 16, Park, Park2 and Kim teach the display apparatus of claim 14, wherein the bias gate stage group comprises a first bias gate stage (Park2, Fig. 11, EBST1), a second bias gate stage (Park2, Fig. 11, EBST3), a third bias gate stage (Park2, Fig. 11, EBST2) configured to receive a first bias gate carry signal of the first bias gate stage, and a fourth bias gate stage (Park2, Fig. 11, EBST4) configured to receive a second bias gate carry signal of the second bias gate stage.
As per claim 17, Park, Park2 and Kim teach the display apparatus of claim 16, wherein the emission stage group (Park2, Fig. 11 suggests wherein drivers are arranged as cascaded stages) comprises, a third first emission stage (Park2, Fig. 11, EBST2 analogue in the emission driver), a fourth first emission stage (Park2, Fig. 11, EBST4 analogue in the emission driver), a first emission stage (Park2, Fig. 11, EBST1 analogue in the emission driver) configured to apply a first emission carry signal to the third first emission stage (Park2, Fig. 11, EBST2 analogue in the emission driver), a second emission stage (Park2, Fig. 11, EBST3 analogue in the emission driver) configured to apply a second emission carry signal to the fourth first emission stage (Park2, Fig. 11, EBST4 analogue in the emission driver).
As per claim 18, Park, Park2 and Kim teach the display apparatus of claim 16, wherein the pixel comprises: a driving transistor (Park, Fig. 4, T1) comprising a control electrode connected to a first node (Park, Fig. 4, N3), a first electrode connected to a second node (Park, Fig. 4, N1), and a second electrode connected to a third node (Park, Fig. 4, N2); a writing transistor (Park, Fig. 4, T2) configured to apply the data voltage to the second node (Park, Fig. 4, N1) in response to the write gate signal (Park, Fig. 4, GW); a first emission transistor (Park, Fig. 4, T6) configured to connect the third node (Park, Fig. 4, N2) and a fourth node (Park, Fig. 4, N4) in response to the emission signal (Park, Fig. 4, EM); a light-emitting element initialization transistor (Park, Fig. 4, T7) configured to apply a light-emitting element initialization voltage (Park, Fig. 4, VINT2) to the fourth node (Park, Fig. 4, N4) in response to the bias gate signal (Park, Fig. 4, GB); and a light-emitting element (Park, Fig. 4, LE) comprising a first electrode connected to the fourth node (Park, Fig. 4, N4), and a second electrode for receiving a low power voltage (Park, Fig. 4, ELVSS).
As per claim 19, Park, Park2 and Kim teach the display apparatus of claim 18, wherein the gate driver is configured to output a compensation gate signal (Figs. 1 and 4, GC) and an initialization gate signal (Figs. 1 and 4, GI), wherein the pixel further comprises: a compensation transistor (Fig. 4, T3) configured to connect the first node (Park, Fig. 4, N3) and the third node (Park, Fig. 4, N2) in response to the compensation gate signal (Park, Fig. 4, GC); and an initialization transistor (Park, Fig. 4, T4) configured to apply an initialization voltage (Park, Fig. 4, VINT1) to the first node (Park, Fig. 4, N3) in response to the initialization gate signal (Park, Fig. 4, GI), and wherein the gate driver further comprises: a compensation gate stage group for generating the compensation gate signal (Park 2, Fig. 11, each signal is generated by its own stage group), and comprising a compensation gate odd stage group on the first side and a compensation gate even stage group on the second side (Kim, Fig. 3, each driver is separated into odd and even drivers on left and right sides); and an initialization gate stage group for generating the initialization gate signal (Park 2, Fig. 11, each signal is generated by its own stage group), and comprising an initialization gate odd stage group on the second side and an initialization gate even stage group on the first side (Kim, Fig. 3, each driver is separated into odd and even drivers on left and right sides).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JOSE R SOTO LOPEZ/ Primary Examiner, Art Unit 2622
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