Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/17/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5-7, 12-14, and 19-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As per claims 5, 12, and 19:
It is unclear whether "the second part of the serial data" is decoded in the decoding operation or before executing the decoding operation in Claim 5, Claim 12, and Claim 19. Claim 5, Claim 12, and Claim 19 recite "in the decoding operation… execute the decoding operation on a second part of the serial data" and "before executing the decoding operation, the second part has been decoded".
As per claims 6, 13, and 20:
It is unclear whether "the first part of the serial data" is decoded in the decoding operation or before executing the decoding operation in Claim 6, Claim 13, and Claim 20. Claim 5, Claim 12, and Claim 19 recite "in the decoding operation… execute the decoding operation on a first part of the serial data" and Claim 6, Claim 13, and Claim 20 recite "before executing the decoding operation, the first part has been decoded".
Any claim not rejected above is rejected due to its dependency on a rejected claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 4-7, 8, 9, 11-14, and 15, 16, and 18-21 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US Pat. Pub. 20200266830; hereinafter referred to as Kim1) in view of Kim et al. (US Pat. Pub. 20250219658; foreign priority filed 12/28/2023; hereinafter referred to as Kim2).
As per claims 1, 8, and 15:
Kim1 teaches a decode control method, a memory storage device, and a memory control circuit unit (Kim1 par. 0238, memory system 2000 and memory device 2200), comprising:
a connection interface unit, coupled to a host system;
a rewritable non-volatile memory module; and
a memory control circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module (Kim1 par. 0240-0241, memory controller 2100 coupled to host interface 2110 and memory device 2200),
wherein the memory control circuit unit is configured to:
in response to a first decoding operation executed according to write data and first parity data failing, read second parity data (Kim1 par. 0253, read second parity data in response to a first error correction decoding using read values failing),
wherein the memory control circuit unit comprises a decoding circuit (Kim1 par. 0261, error correction circuit 2150 includes an error correction decoder 2154), and the decoding circuit is configured to:
execute the second decoding operation according to the second parity data (Kim1 par. 0104, perform a second error correction decoding using second parity data); and
execute a third decoding operation according to the write data, the first parity data, and the second parity data (Kim1 par. 0106-0109, perform a third error correction decoding using first parity data and second parity data).
Kim1 does not explicitly disclose in response to a second decoding operation being successful, increase a log likelihood ratio corresponding to the second parity data. However, Kim2 discloses in response to a second decoding operation being successful, increase a log likelihood ratio corresponding to the second parity data (Kim2 par. 0004, when decoding is properly performed, LLRs gradually increase in magnitude).
Kim1 and Kim2 are analogous arts because they are in the same field of endeavor of decoding. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Kim2’s increasing a LLR in response to a successful decoding operation with the method, memory storage device, and memory control circuit unit of Kim1. This modification would have been obvious to one of ordinary skill in the art at the time of filing because it allows for accurate and rapid decoding (Kim2 par. 0005).
As per claims 2, 9, and 16:
Kim1 and Kim2 further teach the decode control method of claim 1, the memory storage device according to claim 8, and the memory control circuit unit of claim 15, wherein the memory control circuit unit is further configured to: in response to the first decoding operation failing, reduce a log likelihood ratio corresponding to the write data and a log likelihood ratio corresponding to the first parity data (Kim2 par. 0114, when comparison data is 1 (when signs are different), generate a LLR having a magnitude less than when the case where the signs are the same. Please note, when the signs are different, decoding failed and when the signs are the same, decoding is successful as stated in Kim2 par. 0004).
As per claims 4, 11, and 18:
Kim1 and Kim2 further teach the decode control method of claim 1, the memory storage device according to claim 8, and the memory control circuit unit of claim 15, wherein the memory control circuit unit is further configured to: record decoding results of the first decoding operation and the second decoding operation (Kim2 par. 0105, buffers store LLRs of first and second decoding operations); and adjust the log likelihood ratio according to the decoding result (Kim2 par. 0106-0107, LLR adjuster adjusts the LLR according to the LLRs stored in the buffers).
As per claims 5, 12, and 19:
Kim1 teaches a decode control method for a rewriteable non-volatile memory module, a memory storage device, and a memory control circuit unit (Kim1 par. 0238, memory system 2000 and memory device 2200), comprising:
a connection interface unit, coupled to a host system;
a rewritable non-volatile memory module; and
a memory control circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module (Kim1 par. 0240-0241, memory controller 2100 coupled to host interface 2110 and memory device 2200),
wherein the memory control circuit unit comprises a decoding circuit (Kim1 par. 0261, error correction circuit 2150 includes an error correction decoder 2154), and the decoding circuit is configured to:
execute a decoding operation according to serial data; and
in the decoding operation, execute the decoding operation on a first part of the serial data using a first log likelihood ratio, and execute the decoding operation on a second part of the serial data using a second log likelihood ratio (Kim1 par. 0154, first sub-error correction decoding corresponding to a first part codeword C5 and a second sub-error correction decoding corresponding to a second part codeword C3),
wherein the first log likelihood ratio is derived from a first lookup table, and the second log likelihood ratio is derived from a second lookup table (Kim1 par. 0153-0154, select values corresponding to a first part codeword C5 as initial values for the first sub-error correction decoding and select values corresponding to the second part codeword C3 as initial values for the second sub-error correction decoding).
Kim1 does not explicitly disclose wherein before executing the decoding operation, the second part has been decoded and decoding is successful. However, Kim2 discloses wherein before executing the decoding operation, the second part has been decoded and decoding is successful (Kim2 par. 0080, before executing a first decoder, receive a LLR from a second decoder, which means the second decoding operation is completed).
Kim1 and Kim2 are analogous arts because they are in the same field of endeavor of decoding. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Kim2’s completing a second decoding operation with the method, memory storage device, and memory control circuit unit of Kim1. This modification would have been obvious to one of ordinary skill in the art at the time of filing because it allows for accurate and rapid decoding (Kim2 par. 0005).
As per claims 6, 13, and 20:
Kim1 and Kim2 further teach the decode control method of claim 5, memory storage device according to claim 12, and the memory control circuit unit of claim 19 wherein before executing the decoding operation, the first part has been decoded and decoding fails (Kim2 par. 0084, before executing the second decoder, receive a LLR from the first decoder, which means the first decoding operation is completed).
As per claims 7, 14, and 21:
Kim1 and Kim2 further teach the decode control method of claim 5, memory storage device according to claim 12, and the memory control circuit unit of claim 19, wherein the first part and the second part are read from different physical units (Kim1 par. 0273, plurality of partial codewords are stored in different storage areas).
Claims 3, 10, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kim1-Kim2 in further view of Huang et al. (US Pat. Pub. 20250208947; foreign priority filed 12/22/2023; hereinafter referred to as Huang).
As per claims 3, 10, and 17:
Kim1 and Kim2 further teach the decode control method of claim 1, the memory storage device according to claim 8, and the memory control circuit unit of claim 15, wherein the memory control circuit unit is further configured to: in response to a fourth decoding operation being successful, increase a log likelihood ratio corresponding to the third parity data (Kim2 par. 0004), and the decoding circuit is further configured to: execute the fourth decoding operation according to the third parity data (Kim1 par. 0087, first sub-error correction decoding, interpreted as a fourth error correction decoding); and execute a fifth decoding operation according to the write data, the first parity data, the second parity data, and the third parity data (Kim1 par. 0090, second sub-error correction decoding, interpreted as a fifth error correction decoding).
Kim1 and Kim2 do not explicitly disclose in response to the third decoding operation failing, read third parity data. However, Huang discloses in response to the third decoding operation failing, read third parity data (Huang par. 0110, first single-frame decoding performed again is referred to as third single-frame decoding. Please note if the single-frame decoding fails, read parity data from physical units as stated in Huang par. 0090-0091).
Kim1, Kim2, and Huang are analogous arts because they are in the same field of endeavor of decoding. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Huang’s reading third parity data after a third single-frame decoding fails with the method, memory storage device, and memory control circuit unit of Kim1-Kim2. This modification would have been obvious to one of ordinary skill in the art at the time of filing because it improves the decoding success rate for decoding data frames and increases the efficiency and correctness of the reading operations (Huang par. 0130).
Conclusion
The additional prior arts not made of record and have not been relied upon are considered pertinent to applicant’s disclosure as follows:
Yang et al. (US Pat. Pub. 20250125820) discloses a storage device including a nonvolatile memory device and a controller configured to perform first error correction decoding and second error correction decoding. Yang further discloses accelerated error correction by adjusting the log-likelihood ratios.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEFFREY A YANG whose telephone number is (703)756-1447. The examiner can normally be reached Monday - Friday 8:30 a.m. - 5:30 p.m. PST.
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/JEFFREY ANDREW YANG/Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111
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