DETAIL ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. The instant application having application No. 19/178,410 has a total of 20 claims pending in the application; there are 3 independent claim and 17 dependent claims, all of which are ready for examination by the examiner.
INFORMATION CONCERNING DRAWING:
3. The applicant’s drawings submitted on 04/14/2025 are acceptable for examination purposes.
RELEVANT PRIOR ART THE EXAMINER:
4. The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c).
Cai et al. (US 20150178149 A1) teaches “…Some non-volatile memory die, such as flash die, generally enable multi-plane operations--operating on one or more of the planes in parallel--which improves bandwidths. For this reason, the term NVM block as used herein generally refers to a multi-plane block, such as one block from each of the planes, and the term page as used herein generally refers to a multi-plane page, such as one page from each of the planes. In various embodiments, super-blocks may comprise one or more multi-plane blocks from each die. The super-blocks in turn comprise a plurality of super-pages. A super-page comprises 1 (multi-plane) page from each of the (multi-plane) blocks in the super-block...” (par. 0030)).
Parry et al. (US 20230051212 A1) teaches “… For example, the user area 435 may include the dies 405-a and 405-b, the planes 410, the pages 415, and a physical block 440, which may be examples of the corresponding components described in FIG. 3. Generally, the mapping scheme 400 may illustrate an example of an L2L table 420 that supports logic remapping techniques...” (par. 0083).
Opastrakoon et al. (US 11507304 B1) teaches “…a page on each logical unit of a memory device, and each page can be associated with a different wordline of the memory device. The memory sub-system can store consecutively-received host data items on consecutive logical units in pages having page numbers that differ by an offset value…(col. 3, lines 34-39)
INFORMATION CONCERNING CLAIMS:
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 7, 10, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. “Lee” (US 2024/0296126 A1) in view of Zhang “Zhang” (US 2016/0179386 A1).
5. Regarding claim 1, Lee teaches or suggests:
“A system (e.g., ¶ 0001) comprising: a memory device;” (e.g., Fig. 1, ¶ 0027, memory device 100).
“and a processing device, operatively coupled with the memory device, to perform operations comprising: receiving a request to write data to the memory device, the request comprising a data item and a logical address;” (e.g., Fig. 1, ¶ 0028, the memory controller 110 may comprise a processing circuit such as a microprocessor 112; ¶ 0029, The memory controller 110 receives the plurality of host commands and the logical addresses, and translates the plurality of host commands into memory operating commands (which may be referred to as operating commands, for brevity), respectively, and further controls the NV memory 120 with the operating commands to perform reading or writing/programing upon the memory units or data pages of specific physical addresses within the NV memory 120).
“writing the data to the page set;” (e.g., Fig. 4, ¶ 0047, in response to at least one write command (e.g., one or more write command) from the host device 50, the memory controller 110 may store data from the host device 50 into the pages of the superblock (XB) #0, and more particularly, perform the set of table-related processing operations with respect to the aforementioned at least one active block (e.g., the first active block) such as the superblock (XB) #0 (e.g., the set of corresponding blocks (BLK) #0 therein)).
“and modifying, in an address translation data structure (ATDS), a logical address mapping of a translation unit (TU) associated with the page set.” (e.g., Fig. 1, ¶ 0029, the memory controller 110 may generate or update at least one logical-to-physical (L2P) address mapping table to manage the relationships between the physical addresses and the logical addresses; Fig. 4, ¶ 0047, the temporary L2P address mapping table 116T may comprise multiple L2P table entries as shown in FIG. 4. The multiple L2P table entries may carry multiple physical addresses of the pages of the superblock (XB) #0…where any physical address among the multiple physical addresses may comprise a PBA and a PPA, and the PBA and the PPA may be located in multiple higher bits (e.g., a set of consecutive bits comprising the MSB) and multiple lower bits (e.g., a set of consecutive bits comprising the LSB) of the physical address; Fig. 9 and its corresponding text descriptions). The L2P mapping table 116T in Fig. 4 represents address translation data structure (ATDS) and each entry in table translate a logical address to physical block address and physical page address of page group (e.g., set) or super-page.
However, Lee does not expressly teach while:
Zhang discloses: “allocating a plurality of pages of the memory device to a page set, wherein the plurality of pages are associated with a same block of the memory device and sequentially numbered within the same block;” (e.g., Fig. ¶ 0049, FIG. 2 is a simplified representation of a physical memory circuit M. Each memory circuit (typically a packaged product) comprises a plurality of semiconductor chips C. Each chip C may have a plurality of memory pages P, each page having a physical block address (PBA) and configured so as to form blocks B). Figure 2 of Zhang teaches/shows the packaged memory M comprises a plurality chips (e.g., 4 chips C1 – C4). Each chip comprises 4 blocks (e.g., B1 – B4) and 4 pages (e.g., P1 -P4) allocated to each of the memory blocks.
Disclosures by Lee and Zhang are analogous because they are in the same field of endeavor and/or solving a similar or common problem.
It would have been obvious to a person of having ordinary skill in the art before the effective filing date of the claimed invention to modify the mapping table management of a memory device taught by Lee to include the sequentially allocating page number to the memory block disclosed by Zhang.
The motivation for including the sequentially allocating page number as taught by paragraph [0006] of Zhang is to prevent the memory from being filled.
Therefore, it would have been obvious to combine teaching of Zhang with Lee to obtain the invention as specified in the claim.
6. Regarding claim 10, Lee teaches or suggests:
“A method (e.g., ¶ 0001) comprising: receiving a request to write data to a memory device, the request comprising a data item and a logical address;” (e.g., Fig. 1, ¶ 0028, the memory controller 110 may comprise a processing circuit such as a microprocessor 112; ¶ 0029, The memory controller 110 receives the plurality of host commands and the logical addresses, and translates the plurality of host commands into memory operating commands (which may be referred to as operating commands, for brevity), respectively, and further controls the NV memory 120 with the operating commands to perform reading or writing/programing upon the memory units or data pages of specific physical addresses within the NV memory 120).
“writing the data to the page set;” (e.g., Fig. 4, ¶ 0047, in response to at least one write command (e.g., one or more write command) from the host device 50, the memory controller 110 may store data from the host device 50 into the pages of the superblock (XB) #0, and more particularly, perform the set of table-related processing operations with respect to the aforementioned at least one active block (e.g., the first active block) such as the superblock (XB) #0 (e.g., the set of corresponding blocks (BLK) #0 therein)).
“and modifying, in an address translation data structure (ATDS), a logical address mapping of a translation unit (TU) associated with the page set.” (e.g., Fig. 1, ¶ 0029, the memory controller 110 may generate or update at least one logical-to-physical (L2P) address mapping table to manage the relationships between the physical addresses and the logical addresses; Fig. 4, ¶ 0047, the temporary L2P address mapping table 116T may comprise multiple L2P table entries as shown in FIG. 4. The multiple L2P table entries may carry multiple physical addresses of the pages of the superblock (XB) #0…where any physical address among the multiple physical addresses may comprise a PBA and a PPA, and the PBA and the PPA may be located in multiple higher bits (e.g., a set of consecutive bits comprising the MSB) and multiple lower bits (e.g., a set of consecutive bits comprising the LSB) of the physical address; Fig. 9 and its corresponding text descriptions). The L2P mapping table 116T in Fig. 4 represents address translation data structure (ATDS) and each entry in table translate a logical address to physical block address and physical page address of page group (e.g., set) or super-page.
However, Lee does not expressly teach while:
Zhang discloses: “allocating a plurality of pages of the memory device to a page set, wherein the plurality of pages are associated with a same block of the memory device and sequentially numbered within the same block;” (e.g., Fig. ¶ 0049, FIG. 2 is a simplified representation of a physical memory circuit M. Each memory circuit (typically a packaged product) comprises a plurality of semiconductor chips C. Each chip C may have a plurality of memory pages P, each page having a physical block address (PBA) and configured so as to form blocks B). Figure 2 of Zhang teaches/shows the packaged memory M comprises a plurality chips (e.g., 4 chips C1 – C4). Each chip comprises 4 blocks (e.g., B1 – B4) and 4 pages (e.g., P1 -P4) allocated to each of the memory blocks. The motivation for combining is based on the same rational presented for rejection of claim 1.
7. Regarding claim 16, Lee teaches or suggests:
“A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device (e.g., ¶ 0028, the microprocessor 112 is arranged to execute the program code 112C to control the access of the NV memory 120), cause the processing device to perform operations comprising: receiving a request to write data to a memory device, the request comprising a data item and a logical address;” (e.g., Fig. 1, ¶ 0028, the memory controller 110 may comprise a processing circuit such as a microprocessor 112; ¶ 0029, The memory controller 110 receives the plurality of host commands and the logical addresses, and translates the plurality of host commands into memory operating commands (which may be referred to as operating commands, for brevity), respectively, and further controls the NV memory 120 with the operating commands to perform reading or writing/programing upon the memory units or data pages of specific physical addresses within the NV memory 120).
“writing the data to the page set;” (e.g., Fig. 4, ¶ 0047, in response to at least one write command (e.g., one or more write command) from the host device 50, the memory controller 110 may store data from the host device 50 into the pages of the superblock (XB) #0, and more particularly, perform the set of table-related processing operations with respect to the aforementioned at least one active block (e.g., the first active block) such as the superblock (XB) #0 (e.g., the set of corresponding blocks (BLK) #0 therein)).
“and modifying, in an address translation data structure (ATDS), a logical address mapping of a translation unit (TU) associated with the page set.” (e.g., Fig. 1, ¶ 0029, the memory controller 110 may generate or update at least one logical-to-physical (L2P) address mapping table to manage the relationships between the physical addresses and the logical addresses; Fig. 4, ¶ 0047, the temporary L2P address mapping table 116T may comprise multiple L2P table entries as shown in FIG. 4. The multiple L2P table entries may carry multiple physical addresses of the pages of the superblock (XB) #0…where any physical address among the multiple physical addresses may comprise a PBA and a PPA, and the PBA and the PPA may be located in multiple higher bits (e.g., a set of consecutive bits comprising the MSB) and multiple lower bits (e.g., a set of consecutive bits comprising the LSB) of the physical address; Fig. 9 and its corresponding text descriptions). The L2P mapping table 116T in Fig. 4 represents address translation data structure (ATDS) and each entry in table translate a logical address to physical block address and physical page address of page group (e.g., set) or super-page.
However, Lee does not expressly teach while:
Zhang discloses: “allocating a plurality of pages of the memory device to a page set, wherein the plurality of pages are associated with a same block of the memory device and sequentially numbered within the same block;” (e.g., Fig. ¶ 0049, FIG. 2 is a simplified representation of a physical memory circuit M. Each memory circuit (typically a packaged product) comprises a plurality of semiconductor chips C. Each chip C may have a plurality of memory pages P, each page having a physical block address (PBA) and configured so as to form blocks B). Figure 2 of Zhang teaches/shows the packaged memory M comprises a plurality chips (e.g., 4 chips C1 – C4). Each chip comprises 4 blocks (e.g., B1 – B4) and 4 pages (e.g., P1 -P4) allocated to each of the memory blocks. The motivation for combining is based on the same rational presented for rejection of claim 1.
8. Regarding claim 7, Lee further teaches:
“responsive to modifying, in the ATDS, the logical address mapping of the TU associated with the page set (e.g., ¶ 0036, updating one or more L2P table entries in the temporary L2P address mapping table 116T), modifying a valid translation unit count (VTC) associated with the memory device.” (e.g., ¶ 0039, update valid page count table).
Claim 8, 14, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Zhang as applied to claim 1 above, and further in view of SHIN “Shin” (US 2024/0012563 A1).
9. Regarding claims 8, 14, and 20, Lee in view of Zhang teaches all limitation recites in claims 1, 10, and 16 but does not expressly teach while Shin discloses:
“writing the data to a write data buffer of the memory device; and releasing the write data buffer.” (e.g., ¶ 0074, the controller can delete or release the write data stored in the write buffer).
Disclosures by Lee, Zhang, and Shin are analogous because they are in the same field of endeavor and/or solving a similar or common problem.
It would have been obvious to a person of having ordinary skill in the art before the effective filing date of the claimed invention to modify the mapping table management of a memory device taught by Lee to include the sequentially allocating page number to the memory block disclosed by Zhang; furthermore to include the releasing data in write buffer taught by Shin..
The motivation for including the sequentially allocating page number as taught by paragraph [0006] of Zhang is to prevent the memory from being filled; furthermore, the motivation for releasing data stored in the buffer as taught by paragraph [0074} of Shin is to increase utilization of memory resources..
Therefore, it would have been obvious to combine teachings of Shin and Zhang with Lee to obtain the invention as specified in the claim.
Allowable Subject Matter
10. Claims 2-6, 9, 11-13, 15, and 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Direction OF FUTURE CORRESPONDENCES:
11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HASHEM FARROKH whose telephone number is (571)272-4193. The examiner can normally be reached Monday through Friday from 8:30 am - 5:00 pm.
12. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Mr. Tim Vo can be reached on (571)272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HASHEM FARROKH/Primary Examiner, Art Unit 2138
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