DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the response to this Office action, the Office respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Office in prosecuting this application.
The Office has cited particular figures, elements, paragraphs and/or columns and line numbers in the references as applied to the claims for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant, in preparing the responses, to fully consider each of the cited references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage disclosed by the Office.
Priority
2. Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, or 365(c) is acknowledged.
Information Disclosure Statement
3. The information disclosure statement (IDS) submitted on 04/15/2025 is being considered by the Examiner.
Disposition of the Claims
4. The instant application was effectively filed on July 29, 2024, wherein claim 6 is currently canceled and claims 1-5 and 7-20 are pending.
Response to Arguments
Applicant’s arguments filed 06/15/2026 have been considered but are moot in view of new grounds of rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under pre-AIA 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3, 7, 9, 12, 19 and 20 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Kim et al. US PG-PUB 20230230536 A1 (hereinafter Kim) in view of Yang US PG-PUB 20230122487 A1 (hereinafter Yang).
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Regarding claim 1, Kim teaches A pixel circuit (Fig. 7b) comprising: a first transistor comprising a P-type transistor comprising a control electrode connected to a first node (Fig. 7b; gate electrode of transistor T6 connected to node A), a first electrode connected to a second node (Fig. 7b; transistor T6 connected to node N2), and a second electrode connected to a third node (Fig. 7b; transistor T6 connected to node N3); a second transistor configured to apply a data voltage to the first transistor (Fig. 7b and Para. [0206]; applies the PWM data voltage Vsig(m)_R/G/B from the data signal line to the node A through the turned-on transistor T3); a third transistor comprising an N-type transistor connected to the first node and to the third node (Fig. 7b; transistor T4 connected to node N3); a seventh transistor comprising a P-type transistor comprising a control electrode connected to a fourth node (Fig. 7b; gate electrode of transistor T16 connected to node B), a first electrode connected to a fifth node (Fig. 7b; transistor T16 connected to node N5), and a second electrode connected to a sixth node (Fig. 7b; transistor T16 connected to node N6); an eighth transistor configured to apply a second data voltage to the seventh transistor (Fig. 7b and Para. [0211]; applies the VPAM_R/G/B may be applied to the node B through the turned-on transistor T13 to transistor T16); a ninth transistor comprising an N-type transistor connected to the fourth node and to the sixth node (Fig. 7b; see transistor T14); a twelfth transistor comprising an N-type transistor configured to apply a first initialization voltage to the fourth node (Fig. 7b; transistor T11); and a light-emitting element configured to emit light based on the data voltage and the second data voltage, and configured to sequentially emit light in a unit of a pixel row (Fig. 7b and accompanying para’s; light-emitting element 120).
Kim fails to further disclose apply a first initialization voltage to the fourth node is in response to a second initialization signal and a thirteenth transistor comprising a control electrode configured to receive an emission signal, a first electrode connected to an anode electrode of the light-emitting element, and a second electrode configured to receive a second initialization voltage to initialize the anode electrode of the light-emitting element.
However, in the same field of pixel circuit, Yang teaches applying a first initialization voltage to the node in response to a second initialization signal (Fig. 3 and Para. [0078]; applying initialization signal Vint in response to initialization signal GI) and a thirteenth transistor comprising a control electrode configured to receive an emission signal (Fig. 3; gate electrode of transistor T7 connected to emission EM), a first electrode connected to an anode electrode of the light-emitting element (Fig. 3; first electrode of T7 is connected to anode of light emitting element EE), and a second electrode configured to receive a second initialization voltage to initialize the anode electrode of the light-emitting element (Fig. 3 and Para. [0079]; second electrode of transistor T7 is configured to received initialization voltage Vaint to initialize the anode of light emitting element EE)
Thus, it would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to combine the teachings of Kim with the teachings as taught by Yang, in order to improved display quality Yang-(Para. [0085]).
Regarding claim 3, Kim as modified by Yang teaches The pixel circuit of claim 1, Kim teaches further comprising a first capacitor comprising a first electrode configured to receive a sweep signal, and a second electrode connected to the first node (Fig. 7b; capacitor C1).
Regarding claim 7, Kim as modified by Yang teaches The pixel circuit of claim 1, Kim teaches further comprising a second capacitor comprising a first electrode configured to receive a second power voltage (Fig. 7b; capacitor C2 receives voltage VDD_PWM), and a second electrode connected to the fourth node (Fig. 7b; capacitor C2 connected to node B).
Regarding claim 9, Kim as modified by Yang teaches The pixel circuit of claim 1, Kim further teaches wherein the second transistor comprises an N-type transistor, and wherein the eighth transistor comprises an N-type transistor (See Fig. 7b and Para. [0084]; first to tenth transistors T1 to T10 may be one of a P-type transistor and an N-type transistor).
Regarding claim 12, Kim as modified by Yang teaches The pixel circuit of claim 1, Kim further teaches wherein the second transistor comprises a P-type transistor, and wherein the eighth transistor comprises a P-type transistor (Fig. 7b and Para. [0084]; first to tenth transistors T1 to T10 is a P-type transistor).
Regarding claim 19, Kim teaches A display apparatus comprising: a display panel (Para. [0022]; a display apparatus includes: a display panel) comprising a pixel circuit (Para. [0022], Fig’s. 7b, 13a; a display apparatus includes: a display panel including a pixel array in which pixels including a inorganic light-emitting elements are arranged in a row lines and sub-pixel circuits provided for each of the inorganic light-emitting elements and are configured to provide a driving current to the inorganic light-emitting elements); a gate driver configured to output a gate signal to the pixel circuit (Fig. 13a; gate driver 520); and a data driver configured to output a data voltage to the pixel circuit (Fig. 13a; data driver 510), wherein the pixel circuit comprises: a first transistor comprising a P-type transistor comprising a control electrode connected to a first node (Fig. 7b; gate electrode of transistor T6 connected to node A), a first electrode connected to a second node (Fig. 7b; transistor T6 connected to node N2), and a second electrode connected to a third node (Fig. 7b; transistor T6 connected to node N3); a second transistor configured to apply the data voltage to the first transistor (Fig. 7b and Para. [0206]; applies the PWM data voltage Vsig(m)_R/G/B from the data signal line to the node A through the turned-on transistor T3); a third transistor comprising a N-type transistor connected to the first node and to the third node (Fig. 7b; transistor T4 connected to node N3); a seventh transistor comprising a P-type transistor comprising a control electrode connected to a fourth node (Fig. 7b; gate electrode of transistor T16 connected to node B), a first electrode connected to a fifth node (Fig. 7b; transistor T16 connected to node N5), and a second electrode connected to a sixth node (Fig. 7b; transistor T16 connected to node N6); an eighth transistor configured to apply a second data voltage to the seventh transistor (Fig. 7b and Para. [0211]; applies the VPAM_R/G/B may be applied to the node B through the turned-on transistor 13 to transistor T16); a ninth transistor comprising a N-type transistor connected to the fourth node and to the sixth node (Fig. 7b; see transistor T14); a twelfth transistor comprising a N-type transistor configured to apply a first initialization voltage to the fourth node (Fig. 7b; transistor T11); and a light-emitting element configured to emit light based on the data voltage and the second data voltage, and configured to sequentially emit light in a unit of a pixel row (Fig. 7b and accompanying para’s; light-emitting element 120).
Kim fails to further disclose apply a first initialization voltage to the fourth node is in response to a second initialization signal and a thirteenth transistor comprising a control electrode configured to receive an emission signal, a first electrode connected to an anode electrode of the light-emitting element, and a second electrode configured to receive a second initialization voltage to initialize the anode electrode of the light-emitting element.
However, in the same field of pixel circuit, Yang teaches applying a first initialization voltage to the node in response to a second initialization signal (Fig. 3 and Para. [0078]; applying initialization signal Vint in response to initialization signal GI) and a thirteenth transistor comprising a control electrode configured to receive an emission signal (Fig. 3; gate electrode of transistor T7 connected to emission EM), a first electrode connected to an anode electrode of the light-emitting element (Fig. 3; first electrode of T7 is connected to anode of light emitting element EE), and a second electrode configured to receive a second initialization voltage to initialize the anode electrode of the light-emitting element (Fig. 3 and Para. [0079]; second electrode of transistor T7 is configured to received initialization voltage Vaint to initialize the anode of light emitting element EE)
Thus, it would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to combine the teachings of Kim with the teachings as taught by Yang, in order to improved display quality Yang-(Para. [0085]).
Regarding claim 20, Kim teaches An electronic apparatus comprising: a display panel (Para. [0022]; a display apparatus includes: a display panel) comprising a pixel circuit (Fig’s. 7b; pixel circuit); a gate driver configured to output a gate signal to the pixel circuit (Fig. 13a; gate driver 520); a data driver configured to output a data voltage to the pixel circuit (Fig. 13a; data driver 510); a driving controller configured to control the gate driver and the data driver (Fig. 13a; timing controller 400); and a processor configured to output input image data to the driving controller (Fig. 12, 13a; input image is receives by the timing controller), wherein the pixel circuit comprises: a first transistor comprising a P-type transistor comprising a control electrode connected to a first node (Fig. 7b; gate electrode of transistor T6 connected to node A), a first electrode connected to a second node (Fig. 7b; transistor T6 connected to node N2), and a second electrode connected to a third node (Fig. 7b; transistor T6 connected to node N3); a second transistor configured to apply the data voltage to the first transistor (Fig. 7b and Para. [0206]; applies the PWM data voltage Vsig(m)_R/G/B from the data signal line to the node A through the turned-on transistor T3); a third transistor comprising a N-type transistor connected to the first node and to the third node (Fig. 7b; transistor T4 connected to node N3); a seventh transistor comprising a P-type transistor comprising a control electrode connected to a fourth node (Fig. 7b; gate electrode of transistor T16 connected to node B), a first electrode connected to a fifth node (Fig. 7b; transistor T16 connected to node N5), and a second electrode connected to a sixth node (Fig. 7b; transistor T16 connected to node N6); an eighth transistor configured to apply a second data voltage to the seventh transistor (Fig. 7b and Para. [0211]; applies the VPAM_R/G/B may be applied to the node B through the turned-on transistor 13 to transistor T16); a ninth transistor comprising a N-type transistor connected to the fourth node and to the sixth node (Fig. 7b; see transistor T14); a twelfth transistor comprising a N-type transistor configured to apply a first initialization voltage to the fourth node (Fig. 7b; transistor T11); and a light-emitting element configured to emit light based on the data voltage and the second data voltage, and configured to sequentially emit light in a unit of a pixel row (Fig. 7b and accompanying para’s; light-emitting element 120).
Kim fails to further disclose apply a first initialization voltage to the fourth node is in response to a second initialization signal and a thirteenth transistor comprising a control electrode configured to receive an emission signal, a first electrode connected to an anode electrode of the light-emitting element, and a second electrode configured to receive a second initialization voltage to initialize the anode electrode of the light-emitting element.
However, in the same field of pixel circuit, Yang teaches applying a first initialization voltage to the node in response to a second initialization signal (Fig. 3 and Para. [0078]; applying initialization signal Vint in response to initialization signal GI) and a thirteenth transistor comprising a control electrode configured to receive an emission signal (Fig. 3; gate electrode of transistor T7 connected to emission EM), a first electrode connected to an anode electrode of the light-emitting element (Fig. 3; first electrode of T7 is connected to anode of light emitting element EE), and a second electrode configured to receive a second initialization voltage to initialize the anode electrode of the light-emitting element (Fig. 3 and Para. [0079]; second electrode of transistor T7 is configured to received initialization voltage Vaint to initialize the anode of light emitting element EE)
Thus, it would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to combine the teachings of Kim with the teachings as taught by Yang, in order to improved display quality Yang-(Para. [0085]).
Allowable Subject Matter
Claims 2, 4-5, 8, 10-11 and 13-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
5. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMY ONYEKABA whose telephone number is (571)270-7633. The examiner can normally be reached on 9-5.
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/AMY ONYEKABA/Primary Examiner, Art Unit 2628
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