DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is the initial Office Action based on the application filed 04/16/2025. Claims 1-20 are presented for examination and have been considered below.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,301,252 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the presently claimed subject matter is either encompassed by, or constitutes an obvious variation of, the check-node-data compression subject matter recited in the claims of U.S. Patent No. 12,301,252 B2, as follows:
Present application
US12,301,252
1. A method implemented at an electronic device for compressing check node data, the method comprising: identifying a set of check nodes associated with a block of data; for each of the set of check nodes: determining respective check node data based on a subset of codeword symbols in the block of data, the respective check node data indicating validity of the subset of codeword symbols; and identifying a bit item including a plurality of bits of one or more data items in the respective check node data; determining a set of data bits based on a set of bit items of the set of check nodes; and storing the set of data bits in a memory block, wherein the set of bit items of the set of check nodes has a first number of data bits in total, and the set of data bits has a second number of data bits, the second number being smaller than the first number.
2. The method of claim 1, wherein the plurality of bits of the one or more data items include a set of one or more respective most significant bits (MSBs) of each of the one or more data items.
3. The method of claim 1, wherein for each check node, the subset of codeword symbols corresponds to a set of likelihood data items, each likelihood data item indicating a likelihood of a respective codeword symbol being erroneous, the method further comprising: identifying a first likelihood data item and a second likelihood data item, in accordance with a determination that the second likelihood data item is greater than or equal to the first likelihood data item and less than or equal to remaining likelihood data items of the subset of codeword symbols.
4. The method of claim 3, wherein each likelihood data item of the respective codeword symbol is determined based on a log-likelihood ratio (LLR) of two distinct data combinations.
5. The method of claim 1, wherein for each check node, the check node data of the check node further includes a first index data item identifying one of the subset of codeword symbols corresponding to a first likelihood data item of the check node data.
6. The method of claim 1, wherein each of the subset of codeword symbols corresponds to a respective likelihood data item indicating a likelihood of the respective codeword symbol being erroneous, and wherein the check node data of each of the set of check nodes further includes a sign bit that is a combination of signs of respective likelihood data items of the subset of codeword symbols.
7. The method of claim 1, wherein for each of the subset of check nodes, the respective check node data includes a first likelihood data item and an index data item identifying one of the subsets of codeword symbols corresponding to the first likelihood data item, and the one or more data items include the index data item.
8. The method of claim 7, wherein the subset of check nodes includes 3 check nodes, and for each of the subset of check nodes, the plurality of bits of the one or more data items in the respective check node data includes 2 MSBs of the index data item.
9. The method of claim 1, wherein determining the set of data bits based on the set of bit items further comprises: checking a lookup table to determine the set of data bits based on the set of bit items.
10. The method of claim 1, wherein a predefined equation is applied to determine the set of data bits based on the set of bit items.
11. An electronic device, comprising: one or more processors; memory storing one or more programs, the one or more programs further comprising instructions for: identifying a set of check nodes associated with a block of data; for each of the set of check nodes: determining respective check node data based on a subset of codeword symbols in the block of data, the respective check node data indicating validity of the subset of codeword symbols; and identifying a bit item including a plurality of bits of one or more data items in the respective check node data; determining a set of data bits based on a set of bit items of the set of check nodes; and storing the set of data bits in a memory block, wherein the set of bit items of the set of check nodes has a first number of data bits in total, and the set of data bits has a second number of data bits, the second number being smaller than the first number.
12. The electronic device of claim 11, storing the set of data bits in association with the set of check nodes further comprising: storing the set of data bits and a plurality of remaining bit items of the set of check nodes jointly, the plurality of remaining bit items including a set of remaining bits of the one or more data items in the check node data of each of the set of check nodes.
13. The electronic device of claim11,wherein the set of check nodes includes a single check node, and the one or more data items of the single check node include at least two data items.
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14. The electronic device of claim 13, wherein a lookup table is applied to determine the set of data bits based on the bit item of the single check node.
15. The electronic device of claim 11, wherein the memory block includes a dynamic random access memory (DRAM).
16. A non-transitory computer-readable storage medium storing one or more programs to be executed by one or more processors for compressing check node data, the one or more programs comprising instructions for: identifying a set of check nodes associated with a block of data; for each of the set of check nodes: determining respective check node data based on a subset of codeword symbols in the block of data, the respective check node data indicating validity of the subset of codeword symbols; andidentifying a bit item including a plurality of bits of one or more data items in the respective check node data;determining a set of data bits based on a set of bit items of the set of check nodes; and storing the set of data bits in a memory block, wherein the set of bit items of the set of checknodes has a first number of data bits in total, and the set of data bits has a secondnumber of data bits, the second number being smaller than the first number.
17. The non-transitory computer-readable storage medium of claim16, wherein for each of the set of check nodes: the respective check node data includes a first likelihood data item corresponding to a first codeword symbol and a second likelihood data item corresponding to a second codeword symbol; the one or more data items include the first likelihood data item and the second likelihood data item, and the plurality of bits of the one or more data items includes a third number of MSBs of the first likelihood data item and a fourth number of MSBs of the second likelihood data item; and the first likelihood data item is less than or equal to the second likelihood data item.
18. The non-transitory computer-readable storage medium of claim 17, wherein:the set of check nodes includes 3 check nodes, the set of bititems of the set of check nodes includes 6 bits in total;for each of the set of check nodes, the plurality of bits of the one or more data items has 3 value combinations of MSBs of the first and second likelihood data items;the set of bit items of the set of check nodes has 3x3x3 value combinations of MSBs of the first and second likelihood data items, and the set of data bits has 5 bits for representing the 3x3x3 value combinations; andthe first number is greater than the second number by l.
19. The non-transitory computer-readable storage medium of claim 17, wherein:theset of checknodesincludes5, 6, or 7 checknodes;for each of the set of check nodes, the plurality of bits of the one or more data items have 3 value combinations of MSBs of the first and second likelihood data items; andthe first number is greater than the second number by 2.
20. The non-transitory computer-readable storage medium of claim 16, wherein the plurality of bits of the one or more data items include a set of one or more respective most significant bits (MSBs) of each of the one or more data items.
1. A method implemented at an electronic device for compressing check node data, the method comprising: identifying a plurality of check nodes associated with a block of data, each check node corresponding to a subset of codeword symbols in the block of data and having respective check node data that indicate a likelihood of the subset of codeword symbols being erroneous; for each of a subset of check nodes, identifying a set of most significant bits (MSBs) of one or more data items in the respective check node data; determining a set of data bits based on a plurality of MSB sets of the subset of check nodes, the plurality of MSB sets including the set of MSBs of the one or more data items in the respective check node data of each of the subset of check nodes; and storing, in a memory block allocated to the plurality of check nodes, the set of data bits in association with the subset of check nodes; wherein the plurality of MSB sets has a first number of data bits in total, and the set of data bits has a second number of data bits, the second number being smaller than the first number.
2. The method of claim 1, wherein for each of the subset of check nodes, the respective check node data includes a first likelihood data item and an index data item identifying one of the subsets of codeword symbols corresponding to the first likelihood data item, and the one or more data items include the index data item.
3. The method of claim 1, wherein the subset of check nodes includes 3 check nodes, and for each of the subset of check nodes, the set of MSBs of the one or more data items in the respective check node data includes 2 MSBs of the index data item.
4. The method of claim 1, wherein for each of the subset of check nodes: the respective check node data includes a first likelihood data item corresponding to a first codeword symbol and a second likelihood data item corresponding to a second codeword symbol; the one or more data items include the first likelihood data item and the second likelihood data item, and the set of MSBs includes a third number of MSBs of the first likelihood data item and a fourth number of MSBs of the second likelihood data item.
5. The method of claim 4, wherein the first likelihood data item is less than or equal to the second likelihood data item, and the third number and the fourth number are equal to 1.
6. The method of claim 5, wherein: the subset of check nodes includes 3 check nodes, the plurality of MSB sets of the subset of check nodes includes 6 bits in total; for each of the subset of check nodes, the set of MSBs has 3 value combinations of MSBs of the first and second likelihood data items; and the plurality of MSB sets of the subset of check nodes has 3×3×3 value combinations of MSBs of the first and second likelihood data items, and the set of data bits has 5 bits for representing the 3×3×3 value combinations; and the first number is greater than the second number by 1.
7. The method of claim 5, wherein: the subset of check nodes includes 5, 6, or 7 check nodes; for each of the subset of check nodes, the set of MSBs has 3 value combinations of MSBs of the first and second likelihood data items; and the first number is greater than the second number by 2.
8. The method of claim 1, wherein determining the set of data bits based on the plurality of MSB sets further comprises: identifying a lookup table; identifying a combination of the plurality of MSB sets of the subset of check nodes in the lookup table; and checking the lookup table to determine the set of data bits based on the combination of the plurality of MSB sets.
9. The method of claim 1, wherein determining the set of data bits based on the plurality of MSB sets further comprises: identifying a predefined equation; determining a plurality of input values based on the plurality of MSB sets of the subset of check nodes; determining an output value based on the predefined equation and the plurality of input values; and determining the set of data bits from the output value.
10. The method of claim 1, storing the set of data bits in association with the subset of check nodes further comprising: storing the set of data bits and a plurality of remaining bit sets of the subset of check nodes jointly, the plurality of remaining bit sets including a set of remaining bits of the one or more data items in the check node data of each of the subset of check nodes.
11. An electronic device, comprising: one or more processors; and memory storing one or more programs configured for execution by the one or more processors, the one or more programs comprising instructions for: identifying a plurality of check nodes associated with a block of data, each check node corresponding to a subset of codeword symbols in the block of data and having respective check node data that indicate a likelihood of the subset of codeword symbols being erroneous; for each of a subset of check nodes, identifying a set of most significant bits (MSBs) of one or more data items in the respective check node data; determining a set of data bits based on a plurality of MSB sets of the subset of check nodes, the plurality of MSB sets including the set of MSBs of the one or more data items in the respective check node data of each of the subset of check nodes; and storing, in a memory block allocated to the plurality of check nodes, the set of data bits in association with the subset of check nodes; wherein the plurality of MSB sets has a first number of data bits in total, and the set of data bits has a second number of data bits, the second number being smaller than the first number.
12. The electronic device of claim 11, wherein for each check node. the subset of codeword symbols corresponds to a set of likelihood data items, each likelihood data item indicating a likelihood of a respective codeword symbol being erroneous, the one or more programs comprising instructions for: identifying a first likelihood data item and a second likelihood data item, in accordance with a determination that the second likelihood data item is greater than or equal to the first likelihood data item and less than or equal to remaining likelihood data items of the subset of codeword symbols.
13. The electronic device of claim 12, wherein each likelihood data item of the respective codeword symbol is determined based on a log-likelihood ratio (LLR) that is approximated as follows:
LLR
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where p (|) is a probability of a combination of data values, x is a value stored for the respective codeword symbol, and y is a correct value of the respective codeword symbol.
14. The electronic device of claim 11, wherein for each check node, the check node data of the check node further includes a first index data item identifying one of the subset of codeword symbols corresponding to a first likelihood data item of the check node data.
15. The electronic device of claim 11, wherein each of the subset of codeword symbols corresponds to a respective likelihood data item indicating a likelihood of the respective codeword symbol being erroneous, and wherein the check node data of the check node further includes a sign bit that is a combination of signs of respective likelihood data items of the subset of codeword symbols.
16. A non-transitory computer-readable storage medium storing one or more programs to be executed by one or more processors for compressing check node data, the one or more programs comprising instructions for: identifying a plurality of check nodes associated with a block of data, each check node corresponding to a subset of codeword symbols in the block of data and having respective check node data that indicate a likelihood of the subset of codeword symbols being erroneous; for each of a subset of check nodes, identifying a set of most significant bits (MSBs) of one or more data items in the respective check node data; determining a set of data bits based on a plurality of MSB sets of the subset of check nodes, the plurality of MSB sets including the set of MSBs of the one or more data items in the respective check node data of each of the subset of check nodes; and storing, in a memory block allocated to the plurality of check nodes, the set of data bits in association with the subset of check nodes; wherein each of the plurality of MSB sets has a first number of data bits in total, and the set of data bits has a second number of data bits, the second number being smaller than the first number.
17. The non-transitory computer-readable storage medium of claim 16, wherein for each of the subset of check nodes, the respective check node data includes a first likelihood data item and an index data item identifying one of the subsets of codeword symbols corresponding to the first likelihood data item, and the one or more data items include the index data item.
18. The non-transitory computer-readable storage medium of claim 16, wherein the subset of check nodes includes 3 check nodes, and for each of the subset of check nodes, the set of MSBs of the one or more data items in the respective check node data includes 2 MSBs of the index data item.
19. The non-transitory computer-readable storage medium of claim 16, wherein for each of the subset of check nodes: the respective check node data includes a first likelihood data item corresponding to a first codeword symbol and a second likelihood data item corresponding to a second codeword symbol; the one or more data items include the first likelihood data item and the second likelihood data item, and the set of MSBs includes a third number of MSBs of the first likelihood data item and a fourth number of MSBs of the second likelihood data item.
20. The non-transitory computer-readable storage medium of claim 16, wherein determining the set of data bits based on the plurality of MSB sets further comprises: identifying a lookup table; identifying a combination of the plurality of MSB sets of the subset of check nodes in the lookup table; and checking the lookup table to determine the set of data bits based on the combination of the plurality of MSB sets.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3, 5-7, 9-11, 13, 14, 16, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Richardson et al. (US 2006/0026486 A1) in view of Tomic (US 2006/0290539 A1).
Claim 1: Richardson teaches a method implemented at an electronic device for compressing check node data, the method comprising:
identifying a set of check nodes associated with a block of data (e.g., Richardson teaches an LDPC decoder represented by a Tanner graph having variable nodes corresponding to codeword bits and check nodes corresponding to parity-check constraints. See ¶¶[0002]–[0005]);
for each of the set of check nodes:
determining respective check node data based on a subset of codeword symbols in the block of data (e.g., Richardson further teaches that a particular check node receives messages from the variable nodes connected to that check node and generates/stores check-node state information based upon those incoming messages. See ¶¶[0023]–[0025], [0029]. The subset corresponds to the variable/codeword nodes connected to the particular check node.), the respective check node data indicating validity of the subset of codeword symbols (e.g., Richardson also teaches that LDPC messages represent reliability/likelihood information. See ¶[0011]. The stored check-node state is derived from these reliability messages and therefore conveys information concerning the reliability or validity of the corresponding codeword symbols.); and
identifying a bit item including a plurality of bits of one or more data items in the respective check node data (e.g., Richardson further teaches compressed check-node-state information including: minimum reliability/magnitude; second minimum reliability/magnitude; an index identifying the edge associated with the minimum; and accumulated sign information. See¶¶[0025], [0029], [0049], [0057]); and storing the set of data bits in a memory block, wherein the set of bit items of the set of check nodes has a first number of data bits in total, and the set of data bits has a second number of data bits, the second number being smaller than the first number (e.g., Richardson further teaches storing the reduced check-node state in check-node-state memory and expressly seeks to reduce the number of bits required compared with storage of all check-node messages and generally teaches the claimed relationship in which compressed check-node information requires fewer bits than the original information. See ¶¶[0023], [0033]–[0034], [0055]–[0057]).
Richardson fails to teach determining a set of data bits based on a set of bit items of the set of check nodes. However, Tomic teaches mixed-radix/enumerative coding of a sequence:
A=a_1,a_2,\ldots,a_n,
where each item a_i is restricted to a corresponding number R_i of possible values (e.g., [0230]-[0231]). Tomic further teaches calculating a single index:
I(A)=a_1V_0+a_2V_1+\cdots+a_nV_{n-1},
where the index uniquely represents the joint combination. See Tomic, Appendix B, equations B.1–B.3 and the associated discussion (e.g., [0232-[0233]). Tomic further explains that mixed-radix coding avoids bit-fraction loss resulting from separately representing constrained components in whole numbers of binary bits (e.g., [0096]). Therefore, Tomic teaches “determining a set of data bits based on a set of bit items of the set of check nodes” where the resulting joint representation can require fewer total bits. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to apply Tomic’s joint mixed-radix/enumerative coding to selected portions of Richardson’s compressed check-node-state information in order to identify selected data bits/items from multiple check nodes and to store the resulting representation using fewer bits.
Claim 3: Richardson and Tomic teach the method of claim 1, wherein for each check node, the subset of codeword symbols corresponds to a set of likelihood data items, each likelihood data item indicating a likelihood of a respective codeword symbol being erroneous, the method further comprising: identifying a first likelihood data item and a second likelihood data item, in accordance with a determination that the second likelihood data item is greater than or equal to the first likelihood data item and less than or equal to remaining likelihood data items of the subset of codeword symbols. For instance, Richardson teaches identifying: the minimum incoming reliability/magnitude and the second minimum reliability/magnitude. See ¶¶[0029], [0049].
Claim 5: Richardson and Tomic teach the method of claim 1, wherein for each check node, the check node data of the check node further includes a first index data item identifying one of the subset of codeword symbols corresponding to a first likelihood data item of the check node data. For instance, Richardson expressly teaches storing an index identifying the edge associated with the minimum check-node magnitude. See Richardson ¶¶[0029], [0049], [0057]. Because each edge connects the check node to a corresponding variable node/codeword symbol, the index identifies the codeword symbol associated with the first/minimum likelihood value.
Claim 6: Richardson and Tomic teach the method of claim 1, wherein each of the subset of codeword symbols corresponds to a respective likelihood data item indicating a likelihood of the respective codeword symbol being erroneous, and wherein the check node data of each of the set of check nodes further includes a sign bit that is a combination of signs of respective likelihood data items of the subset of codeword symbols. For instance, Richardson teaches an accumulated sign bit obtained from signs of messages associated with the check node. See ¶¶[0025], [0032], [0057]. Thus, Combining the signs, for example using XOR/parity, is the conventional Min-Sum check-node sign computation taught by Richardson.
Claim 7: Richardson and Tomic teach the method of claim 1, wherein for each of the subset of check nodes, the respective check node data includes a first likelihood data item and an index data item identifying one of the subsets of codeword symbols corresponding to the first likelihood data item, and the one or more data items include the index data item. For instance, Richardson teaches: a first/minimum likelihood data item and an index identifying the edge/variable node associated with that minimum. See ¶¶[0029], [0049], [0057].
Claim 9: Richardson and Tomic teach the method of claim 1, wherein determining the set of data bits based on the set of bit items further comprises: checking a lookup table to determine the set of data bits based on the set of bit items. For instance, Tomic teaches that quantities used in determining an enumerative encoding index may be precomputed and retrieved from a lookup table, and further teaches mapping a plurality of constrained input values into a single enumerative/mixed-radix index. See ¶[0023] and ¶¶[0230]–[0233]. It would have been obvious to one of ordinary skill in the art to implement the Richardson/Tomic compact encoding using a lookup table as taught by Tomic because precomputing the correspondence between permissible input combinations and their encoded representations would avoid repeated calculation and provide a predictable implementation of the known enumerative encoding operation.
Claim 10: Richardson and Tomic teach the method of claim 1, wherein a predefined equation is applied to determine the set of data bits based on the set of bit items. For instance, Tomic teaches a sequence of constrained input values A=a_1,a_2,\ldots,a_n and determining a single encoded index from those values according to a predefined mixed-radix equation:
> I(A)=a_1V_0+a_2V_1+\cdots+a_nV_{n-1}.
> See ¶¶[0231]–[0233].
It would have been obvious to one of ordinary skill in the art to determine the compact representation of Richardson’s selected check-node data items using Tomic’s predefined mixed-radix equation because Tomic expressly teaches the equation as a mechanism for converting multiple constrained input values into a single compact encoded index, thereby predictably reducing representational inefficiency.
Regarding claim 13, Richardson teaches maintaining compressed state information on a per-check-node basis. See Richardson ¶¶[0023]–[0025], [0055]–[0057]. Richardson further teaches that the state associated with each check node includes multiple data items, including at least a minimum magnitude, a second-minimum magnitude, an index identifying the edge associated with the minimum, and sign information. See ¶¶[0029], [0049], [0057]. Thus, Richardson teaches that the one or more data items associated with an individual check node include at least two data items. Richardson does not expressly limit the overall set of check nodes to a single check node. However, because Richardson’s compression and storage operations are defined and performed on a per-check-node basis, it would have been obvious to apply the same disclosed operation to a selected single check node as one instance of the broader multi-check-node system, yielding the predictable result of compressing the multiple data items associated with that selected check node.
Claims 11 and 16 recite the device/computer-readable storage medium limitations that substantially correspond to the method limitations of claim 1. Accordingly, claims 11 and 16 are rejected under 35 U.S.C. § 103 for substantially the same reasons set forth above with respect to the corresponding method claim.
Claim 17 recites the computer-readable storage medium limitations that substantially correspond to the method limitations of claim 3. Accordingly, claim 17 is rejected under 35 U.S.C. § 103 for substantially the same reasons set forth above with respect to the corresponding method claim.
Claim 14 recites the device limitations that substantially correspond to the method limitations of claim 9. Accordingly, claim 14 is rejected under 35 U.S.C. § 103 for substantially the same reasons set forth above with respect to the corresponding method claim.
Claim(s) 2, 4, 8, 12, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Richardson and Tomic as applied to claim 1 above, and further in view of Yang (US 2013/0283117 A1).
Claim 2: Richardson and Tomic teach the method of claim 1, but fail to teach that the plurality of bits of the one or more data items include a set of one or more respective most significant bits (MSBs) of each of the one or more data items. However, Yang is expressly directed to an LDPC decoder and method for reducing memory usage. See ¶[0003]. Yang teaches storing, in place of complete check-node messages: min, submin, index, and sign bits. See ¶[0034]. Yang then expressly teaches further reducing memory by storing a most significant bit portion of information associated with the second minimum rather than the complete second-minimum value. See ¶[0035]. More specifically, Yang teaches: when submin and min are five bits, only two MSBs of the five-bit quantity may be stored.
See ¶[0054]. Therefore, it would have been obvious to a POSITA, before the effective filing date of the claimed invention, to apply Yang’s MSB-based reduced-precision storage to Richardson’s multi-bit check-node data items to further reduce check-node memory.
Claim 4: Richardson and Tomic teach the method of claim 3, but fail to teach that each likelihood data item of the respective codeword symbol is determined based on a log-likelihood ratio (LLR) of two distinct data combinations. However, Yang expressly teaches calculating LLR data using V-node and C-node messages. See ¶¶[0007], [0014]. Therefore, it would have been obvious to a POSITA, before the effective filing date of the claimed invention, to represent Richardson’s check-node reliability quantities as LLR-derived information because LLR is a known and expressly taught reliability representation for LDPC decoding.
Claim 8: Richardson and Tomic teach the method of claim 7, but fail to teach that the subset of check nodes includes 3 check nodes, and for each of the subset of check nodes, the plurality of bits of the one or more data items in the respective check node data includes 2 MSBs of the index data item. However, Yang teaches the general memory-reduction technique of retaining only a reduced number of MSBs from a multi-bit check-node quantity and expressly selects two MSBs from a five-bit check-node quantity. See ¶¶[0052]–[0055]. It would have been obvious to apply the same known bit-width-reduction technique to another stored multi-bit check-node field, namely Richardson’s index, where reduced index precision is acceptable, because doing so predictably reduces memory by discarding lower-order bits. Selecting three check nodes merely represents selection of a finite number of the repeatedly processed check nodes for the joint coding operation.
Claim 20 recites the computer-readable storage medium limitations that substantially correspond to the method limitations of claim 2. Accordingly, claim 20 is rejected under 35 U.S.C. § 103 for substantially the same reasons set forth above with respect to the corresponding method claim.
Claim 12: Richardson and Tomic teach the electronic device of claim 11, but fail to teach the set of data bits in association with the set of check nodes further comprising: storing the set of data bits and a plurality of remaining bit items of the set of check nodes jointly, the plurality of remaining bit items including a set of remaining bits of the one or more data items in the check node data of each of the set of check nodes. However, Richardson teaches a check-node state entry containing plural fields such as minimum, second minimum, index and sign.
Yang similarly teaches an internal register jointly storing:
min;
reduced f(submin−min) information;
index; and
sign information,
rather than storing the complete underlying check-node messages. See ¶[0053]. Thus, Yang expressly shows the relevant memory architecture: one check-node record jointly containing a compressed/reduced field together with unreduced remaining fields. It would have been obvious, after replacing one or more selected Richardson fields with the Tomic-compressed representation, to store the resulting compressed field jointly with the other uncompressed portions in the same check-node record, as taught by Yang, because this preserves the information needed to reconstruct/use the check-node state while reducing only the selected portion.
As per claim 18, as discussed with respect to claim 17, Richardson teaches check-node data including a first minimum reliability value and a second minimum reliability value, i.e., Min1 and Min2, with Min1 being the smallest incoming reliability magnitude and Min2 being the second-smallest. See Richardson ¶¶[0029], [0049], [0057]. Thus, Richardson teaches the relationship:
Min1 \le Min2. Yang similarly teaches storing, for each check node, a first absolute minimum value min, a second absolute minimum value submin, an index, and sign information. Yang ¶¶[0034], [0049]–[0051]. Yang further teaches reducing check-node memory by storing reduced-precision most significant bits of minimum-related check-node information. Yang ¶[0035] teaches storing a most-significant-bit portion in place of the complete second-minimum quantity, and ¶¶[0052]–[0055] expressly teach that, where the relevant minimum quantities are five bits, only a two-bit MSB portion may be stored. Accordingly, Richardson in view of Yang teaches or suggests selecting respective MSBs of the first and second likelihood data items.
Because Richardson/Yang establish:
Min1\le Min2,
when one binary MSB from Min1 and one binary MSB from Min2 are considered, the pair (1,0) cannot occur. The permissible pairs therefore are:
(0,0),\;(0,1),\;(1,1),
i.e., three permissible value combinations per check node.
Richardson and Yang do not expressly teach jointly encoding the respective three-state bit items from multiple check nodes into a smaller common representation. However, Tomic teaches mixed-radix encoding for eliminating losses caused by representing constrained values separately in whole numbers of bits. See Tomic ¶[0230]. Tomic ¶[0231] defines an input sequence of constrained-valued items A=a_1,a_2,\ldots,a_n, each having a corresponding radix R_i, and ¶¶[0232]–[0233] teach mapping that sequence into a single mixed-radix/enumerative index. Tomic further teaches that where an input block has a restricted number of permissible patterns, separately representing that block with a whole number of binary bits creates unused binary patterns and therefore bit-fraction loss. See Tomic ¶¶[0242]–[0246]. Tomic ¶[0253] further teaches reducing the aggregate redundancy where multiple such blocks are jointly represented. Applying Tomic’s teaching to three check nodes, each having three permissible combinations, produces:
3\times3\times3=27 permissible joint combinations.
The uncompressed representation uses two selected bits for each of three check nodes:
3\times2=6 \text{ bits}.
Twenty-seven distinct combinations require only:
\lceil\log_2 27\rceil=5 \text{ bits}.
Thus, the resulting compressed representation has five bits rather than six, such that:
6-5=1.
It therefore would have been obvious to one of ordinary skill in the art to jointly encode the three constrained check-node bit items taught or suggested by Richardson/Yang using Tomic’s mixed-radix technique in order to eliminate unused binary combinations and further reduce check-node storage. The combination yields the predictable result recited in claim 18: three check nodes, three permissible combinations per check node, 27 joint combinations, five compressed bits instead of six, and a one-bit reduction.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Richardson and Tomic as applied to claim 11 above, and further in view of Vanaparthy (US 2021/0013903 A1).
Claim 15: Richardson and Tomic teach the electronic device of claim 11, but fail to teach that the memory block includes a dynamic random access memory (DRAM). However, Vanaparthy teaches an ECC/LDPC memory system and states that the memory may include volatile types such as:
RAM;
Dynamic RAM (DRAM);
DDR SDRAM;
SRAM; etc.
See ¶¶[0021]–[0022].
It would have been obvious to implement Richardson’s check-node-state memory using DRAM because Vanaparthy expressly identifies DRAM as a suitable memory in an ECC/LDPC memory system, yielding the predictable result of storing the decoder information in a known volatile memory technology.
As per claim 19, for the reasons discussed above with respect to claim 18, Richardson teaches first and second minimum likelihood/reliability values satisfying:
Min1\le Min2
(see Richardson ¶¶[0029], [0049], [0057]), while Yang teaches storing reduced-precision MSB portions of such check-node minimum information to reduce memory. See Yang ¶¶[0035], [0052]–[0055]. Accordingly, for each check node the selected Min1/Min2 MSB pair has the three permissible combinations:
(0,0),\;(0,1),\;(1,1).
Tomic teaches jointly encoding multiple constrained-valued items as a mixed-radix/enumerative index rather than storing each item independently in a separately rounded binary field. See Tomic ¶¶[0230]–[0233]. Tomic further explains that restricted-valued items whose number of permissible values is not a power of two produce unused binary patterns when separately stored, and that joint encoding reduces this redundancy. See Tomic ¶¶[0242]–[0246], [0253].
Applying Tomic’s teaching to the claimed 5, 6, or 7 check nodes gives: \lceil\log_2(243)\rceil=8,
\lceil\log_2(729)\rceil=10, and \lceil\log_2(2187)\rceil=12.
Thus, compared with separately storing two bits per check node, the resulting joint representations save exactly two bits for each of the claimed 5-, 6-, and 7-check-node arrangements. It therefore would have been obvious to one of ordinary skill in the art to apply Tomic’s mixed-radix encoding to the three-state check-node bit items taught or suggested by Richardson and Yang in order to eliminate unused binary representations and reduce the amount of check-node-state memory. The predictable result is the claimed arrangement wherein the set includes 5, 6, or 7 check nodes, each check node has three permissible MSB combinations, and the first number of bits exceeds the second number by two.
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/GUERRIER MERANT/Primary Examiner, Art Unit 2111 8/28/2026
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