Prosecution Insights
Last updated: October 01, 2026
Application No. 19/181,739

DISPLAY APPARATUS

Non-Final OA §103
Filed
Apr 17, 2025
Priority
Mar 13, 2018 — RE 10-2018-0029280 +3 more
Examiner
SUTEERAWONGSA, JARURAT
Art Unit
2623
Tech Center
2600 — Communications
Assignee
Samsung Display Co., Ltd.
OA Round
3 (Non-Final)
66%
Grant Probability
Favorable
3-4
OA Rounds
1y 7m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 66% — above average
66%
Career Allowance Rate
296 granted / 445 resolved
+4.5% vs TC avg
Strong +33% interview lift
Without
With
+32.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
11 currently pending
Career history
462
Total Applications
across all art units

Statute-Specific Performance

§101
2.7%
-37.3% vs TC avg
§103
74.2%
+34.2% vs TC avg
§102
9.8%
-30.2% vs TC avg
§112
7.9%
-32.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 445 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 09/03/2026 has been entered. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-9, 13, and 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0033849 A1 to Noh et al. (Noh) and US 2014/0145179 A1 to Yoon et al. (Yoon). As to claim 1, Noh discloses A display apparatus (100) (Fig. 2, Par. 60), comprising: a substrate (110) including a first area (display area), a second area (part of non-display area), and a bending area (another part of non-display area when the display is bent) between the first area (display area) and the second area (non-display area) (Fig. 2, Pars. 49, 55), the bending area bent (Fig. 2, Pars. 49, 55, e.g. a part of the non-display area of the lower substrate 110 may be bent); and a first thin film transistor (130), a second thin film transistor (140), and a storage capacitor (Cst) in the first area (display area) (Fig. 2, Pars. 91-92), wherein the first thin film transistor (130) has a first semiconductor layer (131) (Fig. 2, Pars. 64-65) and a first gate electrode (132) insulated from the first semiconductor layer (130) by a first insulating layer (113) (Fig. 2, Par. 70), a first source electrode (133) and a first drain electrode (134) connected to the first semiconductor layer (131)(Fig. 2, Pars. 69, 88), the second thin film transistor (140) has a second semiconductor layer (141) on a second insulating layer (114) (Fig. 2, Pars. 82, 90), a second gate electrode (142 or 152), a second source electrode (143) and a second drain electrode (144) connected to the second semiconductor layer (141) (Fig. 2, Pars. 71, 74), the second insulating layer (114) is between the first insulating layer (113) and the second semiconductor layer (140) (Figs. 2, 4B, Pars. 82, 134), the storage capacitor (Cst) has a lower electrode (133), an upper electrode (151), and a dielectric layer (storage capacitor layer Cst) between the lower electrode (133) and the upper electrode (151) (Fig. 2, Pars. 91-92), the second semiconductor layer (141) and the lower electrode (133) are arranged on a same layer (e.g. on 114) (Figs. 2, 4B, Par. 134), and the lower electrode includes an oxide semiconductor material (Figs. 2, 4B, Par. 135). Noh does not expressly disclose the second semiconductor layer and the lower electrode are simultaneously formed. Yoon discloses an oxide semiconductor layer (102) and the lower electrode (112 includes oxide semiconductor material) are simultaneously formed and arranged on a same layer (Figs. 2, 5-10, 12, Pars. 41-42, see also Pars. 47, 61, e.g. oxide semiconductor layer is formed on the entire surface then plasma processed to form 102 and 112). Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to have modified Noh with the teaching of Yoon to reduce cost as suggested by Yoon (Par. 81). As to claim 13, Noh teaches the display apparatus of claim 1 above. The limitation of claim 13 is substantially similar to claim 1. Accordingly, claim 13 is rejected based on same analysis as claim 1. Noh further discloses an electronic apparatus (e.g. personal electronic device) comprising: an electronic device (e.g. wearable device) connected to the display apparatus (Par. 11). As to claim 2, Noh discloses the first insulating layer (113) comprises one or more of silicon nitride (SiNx) (Par. 70) (omit or silicon oxide (SiO2), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta20s), hafnium oxide (HfO2), or zinc oxide (ZnO2)). As to claim 3, Noh discloses the second insulating layer (114) comprises one or more of silicon nitride (SiNx) (Par. 77) (omit or silicon oxide (SiO2), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta20s), hafnium oxide (HfO2), or zinc oxide (ZnO2)). As to claim 16, Noh teaches the display apparatus of claims 2 and 3 above. The limitation of claim 16 is substantially similar to claims 2 and 3. Accordingly, claim 16 is rejected based on same analysis as claims 2 and 3. As to claim 4, Noh discloses the first source electrode (133) and the first drain electrode (134) comprise one or more of Ti or Al (Par. 135). As to claim 17, Noh teaches the display apparatus of claim 4 above. The limitation of claim 17 is substantially similar to claim 4. Accordingly, claim 17 is rejected based on same analysis as claim 4. As to claim 5, Noh discloses the first source electrode and the first drain electrode comprise a three-layer structure comprising Ti/Al/Ti (Par. 135). As to claim 18, Noh teaches the display apparatus of claim 5 above. The limitation of claim 18 is substantially similar to claim 5. Accordingly, claim 18 is rejected based on same analysis as claim 5. As to claim 6, Noh discloses the upper electrode (151) of the storage capacitor (Cst) comprises Ti (Pars. 135, 140, e.g. 151 may be formed of the same material as 133). As to claim 19, Noh teaches the display apparatus of claim 6 above. The limitation of claim 19 is substantially similar to claim 6. Accordingly, claim 19 is rejected based on same analysis as claim 6. As to claim 7, Noh discloses the storage capacitor (Cst) overlaps the first gate electrode (132) (Figs. 2, 4C, Par. 92, e.g. lower electrode of Cst 133 partially overlaps gate electrode 132) . As to claim 20, Noh teaches the display apparatus of claim 7 above. The limitation of claim 20 is substantially similar to claim 7. Accordingly, claim 20 is rejected based on same analysis as claim 7. As to claim 8, Noh discloses the second insulating layer (114) is disposed between the first gate electrode (132) and the lower electrode of the storage capacitor (114) (Fig. 2, Pars. 77, 92). As to claim 9, Noh discloses the first semiconductor (131) comprises a silicon semiconductor material (Pars. 67, 112) and the second semiconductor (140) comprises an oxide semiconductor material (Pars. 69, 73). Claim(s) 10, 14, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0033849 A1 to Noh et al. (Noh) and US 2014/0145179 A1 to Yoon et al. (Yoon); in view of US 2017/0170206 A1 to Lee et al. (Lee). As to claim 10, Noh does not expressly disclose the first insulating layer and the second insulating layer are disposed in the first area and the second area, and wherein the first insulating layer and the second insulating layer have openings corresponding to the bending area. Lee discloses the insulating layers (120, 290, 250, 240, 230, 220) are disposed in the first area (display area) and the second area (non-display area) (Fig. 7, Pars. 48, 54-55), and wherein the insulating layers (120, 290, 250, 240, 230, 220) have openings (CH4, CH5) corresponding to the bending area (Figs. 7, 10, Par. 72). Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to have modified Noh with the teaching of Lee to prevent crack from occurring in lines of a bending area as suggested by Lee (Par. 20). As to claim 14, Noh does not expressly disclose an inner wire in the first area and an outer wire in the second area, wherein the electronic device is connected to the display apparatus by the outer wire. Lee discloses an inner wire (150-151) in the first area (display area) and an outer wire (153) in the second area (non-display area) (Figs. 6-7, Pars. 70, 72), wherein the electronic device is connected to the display apparatus by the outer wire (153)(Figs. 6-7, Pars. 70, 72). Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to have modified Noh with the teaching of Lee to enable the display to be connected to an external system thereby provide an improved display device as suggested by Lee (Par. 70). As to claim 15, Noh does not expressly disclose a connection wire connecting the inner wire and the outer wire, and the connection wire is disposed over the bending area. Lee discloses a connection wire (280) connecting the inner wire (150-151) and the outer wire (153) (Figs. 6-7, Pars. 70, 72), and the connection wire is disposed over the bending area (Figs. 6-7, Pars. 70, 72). Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to have modified Noh with the teaching of Lee to enable the display to be connected to an external system thereby provide an improved display device as suggested by Lee (Par. 70). Claim(s) 11 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0033849 A1 to Noh et al. (Noh) and US 2014/0145179 A1 to Yoon et al. (Yoon); in view of US 2017/0170206 A1 to Lee et al. (Lee); further in view of US 2014/0217397 A1 to Kwak et al. (Kwak). As to claim 11, Noh does not expressly disclose the display apparatus of claim 10, further comprising an organic material layer filling the openings. Kwak discloses an organic material layer filling the openings (opening in 269C in NA region) (Fig. 2C, Par. 146). Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to have modified Noh with the teaching of Kwak to minimize the impact of bending of the display device as suggested by Kwak (Par. 145). As to claim 12, Noh as modified a connection wire (220C) disposed on the organic material layer (269C) (Fig. 2C, Par. 145). See claim 11 motivation above. Response to Arguments Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because of the new ground of rejection. Examiner notes that the new claim elements are now addressed by reference Yoon as necessitated by amendments. Please see above for full basis of rejection as taught by Noh in view of Yoon. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2012/0146031 A1 to Lee teaches a display device with the semiconductor layer and the lower electrode of a capacitor formed on the same layer. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARURAT SUTEERAWONGSA whose telephone number is (571)270-7361. The examiner can normally be reached Monday thru Thursday, 8:30AM to 4:00PM, EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached at 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JARURAT SUTEERAWONGSA/Examiner, Art Unit 2623 /CHANH D NGUYEN/Supervisory Patent Examiner, Art Unit 2623
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Prosecution Timeline

Apr 17, 2025
Application Filed
Jan 16, 2026
Non-Final Rejection mailed — §103
Feb 12, 2026
Response Filed
Jun 04, 2026
Final Rejection mailed — §103
Aug 03, 2026
Response after Non-Final Action
Sep 03, 2026
Request for Continued Examination
Sep 08, 2026
Response after Non-Final Action
Sep 23, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12745510
DISPLAY DEVICE
4y 9m to grant Granted Sep 22, 2026
Patent 12737057
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2y 6m to grant Granted Sep 15, 2026
Patent 12730522
SEMANTIC USER INPUT
4y 6m to grant Granted Sep 08, 2026
Patent 12710657
EXTENDED REALITY SYSTEM INCLUDING AI-ASSISTED IMAGE CAPTURE OPTICAL CHARACTER RECOGNITION FOR USE WITH VISUAL AID CORRECTION FOR LOW VISION
1y 7m to grant Granted Aug 18, 2026
Patent 12706036
DEVICES AND METHODS FOR PROVIDING ACCESS TO INTERNAL COMPONENT
5y 0m to grant Granted Aug 11, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
66%
Grant Probability
99%
With Interview (+32.9%)
3y 1m (~1y 7m remaining)
Median Time to Grant
High
PTA Risk
Based on 445 resolved cases by this examiner. Grant probability derived from career allowance rate.

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