Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless -
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, 5 and 7-10 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Kim (Patent Application Publication 2022/0140099).
Claim 1. A memory device comprising: a first bit cell group comprising a first plurality of bit cells (memory device 10 and bitcell group G1 containing bitcells 12-1 through 12-4, Kim [0028], [0040-0041], Fig 1 and 3); and a first peripheral circuit group configured to write data to the first plurality of bit cells and read data from the first plurality of bit cells (I/O Group G2 within I/O block 13; read circuit 13-3 and write circuit 13-4; back-end logic forming a sense amplifier and write driver, Kim [0035,0038,0039,0050,0078] Fig 2 and 6), wherein the first peripheral circuit group comprises a first type transistor and a second type transistor of a different type from the first type transistor (standard cell implementation of the logic cells. With the neighboring pair of WM cells on the left side of Fig 6 arranged side by side along X, Kim [0071,0075,0096] Fig 6), and wherein the first peripheral circuit group comprises a plurality of first standard cells adjacent to each other in a first direction and a first switch cell comprising one of the first type transistor and the second type transistor (power gating cell PG containing one PFET and supplying power to bitline BL under control of write signal CTR21, Kim [0076,0081] Fig 6-7).
Claim 4. The memory device of claim 1, further comprising: a second bit cell group comprising a second plurality of bit cells (G1 groups repeatedly arranges along X, Kim [0040-0041]); and a second peripheral circuit group configured to write data to the second plurality of bit cells and read data from the second plurality of bit cells, wherein the second peripheral circuit group comprises a plurality of second standard cells including the first type transistor and the second type transistor and a second switch cell comprising one of the first type transistor and the second type transistor, and wherein the second peripheral circuit group is adjacent to the first peripheral circuit group in the first direction (multiple G2 groups repeatedly arranged along X, with adjacent active region groups corresponding to different G1 groups, Kim [0050,0066]. Same layouts of active region power rail and signal line groups, Kim [0050]).
Claim 5. The memory device of claim 4, wherein the first switch cell and the second switch cell are adjacent to a boundary between the first peripheral circuit group and the second peripheral circuit group (four PG cell in each G2; G2 layout repeated along X, Kim [0050,0076] Fig 6).
Claim 7. The memory device of claim 1, wherein the first type transistor and the second type transistor are gate-all-around (GAA) transistors (PG transistor may be a GAAFET; WM transistors may be GAAFETs, Kim [0081,0084] Figs 7-8).
Claim 8. The memory device of claim 7, wherein the gate all-around transistors are multi- bridge channel (MBC) transistors (PG transistor may be an MBCFET; WM transistor may be MBCFETs, Kim [0081,0084]).
Claim 9. The memory device of claim 1, wherein the first plurality of bit cells are static random access memory (SRAM) cells (bitcells 12 may be SRAM; Fig 10 SRAM bitcell, Kim [0028,0089]).
Claim 10. The memory device of claim 1, wherein the first type transistor is a P-type transistor (PG includes one PFET, Kim [0081]), and wherein the second type transistor is an N-type transistor (WM includes two NFETs, Kim [0084]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (Patent Application Publication 2022/0140099), in view of Chang (Patent Application Publication 2022/0085005).
Claim 6. Kim teaches the memory device of claim 5, but is silent with respect to wherein types of transistors of the first switch cell and the second switch cell are different from each other.
Chang discloses header cells 102h and footer cells 102f positioned on opposite sides of standard logic cells 104, Chang Fig 1) for the purpose of cutting of power to standard logic cells during standby or sleep mode to save chip power consumption (header and footer switches controlled to cut off the power supply during standby or sleep, Chang Fig 1).
Since Kim and Change are both from the same field of endeavor (memory cells using power gating switch cells), the purpose disclosed by Change would have been recognized in the pertinent art of Kim.
It would have been obvious at the time the invention was made to a person having ordinary skill in the art to use Chang’s complementary PMOS header and NMOS footer switch cell arrangement in Kim’s adjacent peripheral circuit groups for the purposes of cutting of power to standard logic cells during standby or sleep mode to save chip power consumption.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (Patent Application Publication 2022/0140099), in view of Lim (Patent Application Publication 2022/0383948).
Claim 11. Kim teaches the memory device of claim 1, but is silent with respect to wherein the first peripheral circuit group is aligned with the first bit cell group in a second direction perpendicular to the first direction, and wherein a width of the first peripheral circuit group in the first direction and a width of the first bit cell group in the first direction are equal.
Lim discloses a peripheral collum group PCG corresponding to a memory column group MCG, the groups being aligned in Y and having the same width in X (PCG and MCG aligned in the Y-axis direction and have the same width in the X-axis direction) for the purpose of optimizing peripheral region area and performance by arranging standard cells in columns having various heights (standard cells having various heights placed according to driving force, performance, and integration requirements, Lim Summary and Fig 3).
Since Kim and Lim are both from the same field of endeavor (non-volatile semiconductor memory with column layout), the purpose disclosed by Lim would have been recognized in the pertinent art of Kim.
It would have been obvious at the time the invention was made to a person having ordinary skill in the art to use Lim’s matched width memory and column group arrangement in Kim’s G1 and G2 groups for the purposes of optimizing peripheral region arear and performance.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (Patent Application Publication 2022/0140099), in view of Shin (Patent Application Publication 2008/0012424).
Claim 2. Kim teaches the memory device of claim 1, further comprising: a plurality of power rails on a boundary of the plurality of first standard cells, wherein the plurality of power rails are configured to extend in a second direction perpendicular to the first direction (power rails PR1-PR7 separated in Claim and extending in Y, Kim [0046,0069] Fig 3 and Fig 6), but is silent with respect to wherein the plurality of power rails are configured to apply a first power voltage and a second power voltage different from the first power voltage to each of the plurality of first standard cells, and the first switch cell is between a first power rail and a second power rail among the plurality of power rails, wherein the first power rail and the second power rail are adjacent to each other, but is silent with respect to the switch cell revieing an external power voltage transmitting the power voltage onto a power rail supplying the standard cells.
Shing teaches the plurality of power rails are configured to apply a first power voltage and a second power voltage different from the first power voltage to each of the plurality of first standard cells (general standard cell 31 supplied by virtual power voltage rail 311 and ground voltage rail 312, Shin Fig 3), and the first switch cell is between a first power rail and a second power rail among the plurality of power rails (power gating cell 32 switched the connection between power voltage rail 321 and virtual power voltage rail 311, Shin Fig 3), wherein the first power rail and the second power rail are adjacent to each other for the purpose of reducing leakage current and power consumption in standby mode (power gating resources standby leakage and power consumption, Shin Fig 1).
Since Kim and Shin are both from the same field of endeavor (powering and power gating in nonvolatile semiconductor memory), the purpose disclosed by Shin would have been recognized in the pertinent art of Kim.
It would have been obvious at the time the invention was made to a person having ordinary skill in the art to use Shin’s supply to virtual rail power gating cell in Kim’s peripheral standard cell circuitry for the purposes of reducing standby leakage current and power consumption.
Claim 3. The memory device of claim 2, wherein the first switch cell is configured to receive a power voltage from an external source and to transmit the power voltage as the first power voltage to at least one of the first power rail or the second power rail (PMOS source contacted with power voltage rail 321 and supplied with VDD; drain contacted with virtual power voltage rail 311 and supplied with VDD, Shin Fig 3. PMOS transistor 41 having source 412 connected to power voltage rail 42 and drain 413 connected to virtual power voltage rail 43, Shin Fig 4).
Allowable Subject Matter
Claims 12-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Claims 12-17. Wherein the peripheral circuit group is aligned with the bit cell group in a second direction perpendicular to the first direction, and wherein the peripheral circuit group comprises: a plurality of power rails that are spaced apart from each other in the first direction and extend in the second direction, a plurality of first active regions between a first power rail and a second power rail among the plurality of power rails, wherein the plurality of first active regions are spaced apart from each other in the first direction and extend in the second direction and comprise a first transistor and a second transistor having a different type from the first transistor, wherein the first transistor and the second transistor are electrically connected to a first bit cell and a second bit cell, respectively, among the plurality of bit cells, a plurality of second active regions between a third power rail and a fourth power rail among the plurality of power rails, wherein the plurality of second active regions are spaced apart from each other in the first direction and extend in the second direction and comprise a third transistor and a fourth transistor having a different type from the third transistor, wherein the third transistor and the fourth transistor are electrically connected to a third bit cell and a fourth bit cell, respectively, among the plurality of bit cells, and a third active region between the second power rail and third power rail, wherein the second power rail and the third power rail are adjacent to each other, wherein the third active region is spaced apart from the second power rail and the third power rail in the first direction by a same distance in the first direction and extends in the second direction, and wherein the third active region comprises a fifth transistor, in combination with other limitations.
Claims 18-20. A plurality of standard cells having a second width in the first direction different from the first width, wherein the plurality of standard cells are electrically connected to the plurality of bit cells through bit lines, wherein the plurality of standard cells comprise a plurality of active regions, wherein each of the plurality of active regions comprises a first type transistor and a second type transistor different from the first type transistor, wherein a height in the first direction of each of the plurality of standard cells is based on a width of a respective active region of the plurality of active regions in the first direction, and wherein the plurality of standard cells are aligned in the first direction; and a non-standardized cell aligned with the plurality of standard cells in the first direction and having a height equal to a difference between the first width and the second width, in combination with other limitations.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason Lappas whose telephone number is (571) 270-1272. The examiner can normally be reached on M-F 7:30AM-5:00PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON LAPPAS/
Primary Examiner, Art Unit 2827
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