DETAILED ACTION
The Examiner acknowledges the applicant's submission of the amendment dated 8/11/2026.
REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4 and 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Yuan et al (US 2016/0005491) in view of Wong (US 10,468,107).
Regarding Claim 3, Yuan teaches a method of programming a memory cell having a floating gate (“memory cells with charge trapping layers or floating gates,” Paragraph 0141), the method comprising:
applying a first program pulse to the memory cell to place electrons on the floating gate (first program pulse 801 of Fig. 8, which places electrons on a floating gate, Paragraph 0136, also a program pulse applies a “charge [electrons] on the floating gate,” Paragraph 0003), wherein the first program pulse comprises a program voltage that includes a preliminary voltage level in a first portion of the first program pulse (see preliminary voltage level Vpass_nominal in the first portion of program pulse 801 of Fig. 8) and a first voltage level in a second portion of the first program pulse, wherein the first voltage level is greater than the preliminary voltage level, and wherein the first voltage level is applied immediately successive to the preliminary voltage level (see first voltage level Vpgm_initial of pulse 801, shown on Fig. 8 as greater than the preliminary voltage level and applied immediately successive to the preliminary voltage level); and
after applying the first program pulse, applying successive program pulses to the memory cell to place additional electrons on the floating gate, wherein the successive program pulses include the program voltage, and wherein the program voltage increases in voltage level for each one of the successive program pulses relative to a previous one of the successive program pulses or the first program pulse (see successive pulses 802, 803, 804, and 805 of Fig. 8, each including at least a program voltage corresponding to the difference between the peak voltage of each pulse and Vpass_nominal as shown, and the program pulses increase with each successive pulse as shown).
However, the cited prior art does not explicitly teach: after applying the successive program pulses, applying second successive program pulses to the memory cell to place additional electrons on the floating gate until a target program state for the memory cell is achieved, wherein the second successive program pulses include the program voltage, and wherein the program voltage has a fixed voltage level for all of the second successive program pulses, and wherein all the successive program pulses and all of the second successive program pulses have a same duration.
Wong teaches after applying the successive program pulses (successive program pulses 1170-1178 of Fig. 11D), applying second successive program pulses to the memory cell to place additional electrons on the floating gate until a target program state for the memory cell is achieved, wherein the second successive program pulses include the program voltage, and wherein the program voltage has a fixed voltage level for all of the second successive program pulses, and wherein all of the successive program pulses and all of the second successive program pulses have a same duration (see how the pulses on the right of Fig. 11D are at a fixed Vpp max and all pulses have a same duration, C28 L65-C29 L39).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the second successive program pulses of Wong in the cited prior art in order to limit the peak programming current (C28 L65 – C29 L39 of Wong).
Regarding Claim 2, the cited prior art teaches the method of claim 3, comprising: performing a program verify read operation after the first program pulse and after each of the successive program pulses to determine a program state of the memory cell (see verify voltages 811-815 of Fig. 8, Paragraph 0134 of Yuan).
Regarding Claim 4, the cited prior art teaches the method of claim 3, comprising: performing a program verify read operation after each of the second successive program pulses to determine a program state of the memory cell; and determining the target program state for the memory cell is achieved based upon one of the program verify read operations “see verify voltages 811-815 of Fig. 8, Paragraphs 0134-0135 of Yuan).
Claim 10 is the semiconductor device corresponding to the method of claim 2, and is rejected under similar rationale.
Claim 11 is the semiconductor device corresponding to the method of claim 3, and is rejected under similar rationale.
Claim 12 is the semiconductor device corresponding to the method of claim 4, and is rejected under similar rationale.
Claims 5 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Yuan et al (US 2016/0005491) in view of Wong (US 10,468,107) and Moschiano et al (US 2009/0219761).
Regarding Claim 5, the cited prior art teaches the method of claim 3, but does not explicitly teach:
after applying the second successive program pulses and achieving the target program state for the memory cell, applying an extra program pulse to the memory cell to place additional electrons on the floating gate, wherein the extra program pulse includes the program voltage with the fixed voltage level
Moschiano teaches:
after applying the second successive program pulses and achieving the target program state for the memory cell (pulses shown on Fig. 5A), applying an extra program pulse to the memory cell to place additional electrons on the floating gate, wherein the extra program pulse includes the program voltage with the fixed voltage level (“another programming pulse is applied 410 to the word line (i.e., the control gate) of the selected memory cell,” step 410 of Fig. 4 and Paragraph 0031, which happens after verification of step 405 of Fig. 4).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the pulses of Moschiano in the cited prior art in order to ensure the cell is programmed correctly.
Claim 13 is the semiconductor device corresponding to the method of claim 5, and is rejected under similar rationale.
Claims 6-8 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Yuan et al (US 2016/0005491) in view of Moschiano et al (US 2009/0219761).
Regarding Claim 6, Yuan teaches a method of programming a memory cell having a floating gate (“memory cells with charge trapping layers or floating gates,” Paragraph 0141), the method comprising:
applying a first program pulse to the memory cell to place electrons on the floating gate (first program pulse 801 of Fig. 8, which places electrons on a floating gate, Paragraph 0136, also a program pulse applies a “charge [electrons] on the floating gate,” Paragraph 0003), wherein the first program pulse comprises a program voltage that includes a preliminary voltage level in a first portion of the first program pulse (see preliminary voltage level Vpass_nominal in the first portion of program pulse 801 of Fig. 8) and a first voltage level in a second portion of the first program pulse, wherein the first voltage level is greater than the preliminary voltage level, and wherein the first voltage level is applied immediately successive to the preliminary voltage level (see first voltage level Vpgm_initial of pulse 801, shown on Fig. 8 as greater than the preliminary voltage level and applied immediately successive to the preliminary voltage level); and
after applying the first program pulse, applying successive program pulses to the memory cell to place additional electrons on the floating gate, wherein the successive program pulses include the program voltage, and wherein the program voltage increases in voltage level for each one of the successive program pulses relative to a previous one of the successive program pulses or the first program pulse (see successive pulses 802, 803, 804, and 805 of Fig. 8, each including at least a program voltage corresponding to the difference between the peak voltage of each pulse and Vpass_nominal as shown, and the program pulses increase with each successive pulse as shown).
However, Yuan does not explicitly teach: ceasing the applying of the successive program pulses upon achieving a target program state for the memory cell; and after the ceasing, applying an extra program pulse to the memory cell to place additional electrons on the floating gate, wherein the extra program pulse includes the program voltage with a voltage level that is the same as a voltage level of the program voltage in a last one of the successive program pulses.
Moschiano teaches:
ceasing the applying of the successive program pulses upon achieving a target program state for the memory cell (upon achieving a target program state at step 405 of Fig. 4, pulses are ceased at step 406 of Fig. 4); and after the ceasing, applying an extra program pulse to the memory cell to place additional electrons on the floating gate (“another programming pulse is applied 410 to the word line (i.e., the control gate) of the selected memory cell,” step 410 of Fig. 4 and Paragraph 0031), wherein the extra program pulse includes the program voltage with a voltage level that is the same as a voltage level of the program voltage in a last one of the successive program pulses (see the program voltages on the right side of Fig. 5A, where each pulse is at least as large as the previous pulse, and therefore the extra programming pulse includes the program voltage with a voltage level that is the same as a voltage level of the program voltage in a last one of the successive program pulses).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the pulses of Moschiano in the cited prior art in order to ensure the cell is programmed correctly.
Regarding Claim 7, the cited prior art teaches the method of claim 6, comprising: performing a program verify read operation after each of the successive program pulses to determine a program state of the memory cell; and determining the target program state for the memory cell is achieved based upon one of the program verify read operations (see verify voltages 811-815 of Fig. 8, Paragraph 0134 of Yuan).
Regarding Claim 8, the cited prior art teaches the method of claim 7, wherein the ceasing the applying of the successive program pulses is based on the determining the target program state for the memory cell is achieved (step 405 of Fig. 4 of Moschiano, Paragraph 0029).
Claim 14 is the semiconductor device corresponding to the method of claim 6, and is rejected under similar rationale.
Claim 15 is the semiconductor device corresponding to the method of claim 7, and is rejected under similar rationale.
Claim 16 is the semiconductor device corresponding to the method of claim 8, and is rejected under similar rationale.
Claims 17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yuan et al (US 2016/0005491) in view of Wong (US 10,468,107) and Liang et al (US 1021/0110873).
Regarding Claim 17, the cited prior art teaches the method of claim 3, but does not explicitly teach wherein the memory cell comprises: spaced apart source and drain regions formed in a semiconductor substrate, wherein a channel region of the semiconductor substrate extends between the source and drain regions, and wherein the floating gate is disposed over and insulated from, and directly controls a conductivity of, a first portion of the channel region; and a select gate disposed over and insulated from, and directly controls a conductivity of, a second portion of the channel region.
Liang teaches wherein a memory cell comprises: spaced apart source and drain regions formed in a semiconductor substrate, wherein a channel region of the semiconductor substrate extends between the source and drain regions, and wherein the floating gate is disposed over and insulated from, and directly controls a conductivity of, a first portion of the channel region; and a select gate disposed over and insulated from, and directly controls a conductivity of, a second portion of the channel region (“each of the memory cells includes: source and drain regions formed in the substrate and defining a channel region of the substrate extending there between, a floating gate disposed vertically over and insulated from a first portion of the channel region, a select gate disposed vertically over and insulated from a second portion of the channel region,” Claim 1).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the cell structure of Liang in the cited prior art in order to allow for selective erasure of just a portion of a row of memory cell pairs (Paragraph 0012).
Claim 19 is the semiconductor device corresponding to claim 17,and is rejected under similar rationale.
Claims 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yuan et al (US 2016/0005491) in view of Moschiano et al (US 2009/0219761) and Liang et al (US 1021/0110873).
Regarding Claim 18, the cited prior art teaches the method of claim 6, but does not explicitly teach wherein the memory cell comprises: spaced apart source and drain regions formed in a semiconductor substrate, wherein a channel region of the semiconductor substrate extends between the source and drain regions, and wherein the floating gate is disposed over and insulated from, and directly controls a conductivity of, a first portion of the channel region; and a select gate disposed over and insulated from, and directly controls a conductivity of, a second portion of the channel region.
Liang teaches wherein the memory cell comprises: spaced apart source and drain regions formed in a semiconductor substrate, wherein a channel region of the semiconductor substrate extends between the source and drain regions, and wherein the floating gate is disposed over and insulated from, and directly controls a conductivity of, a first portion of the channel region; and a select gate disposed over and insulated from, and directly controls a conductivity of, a second portion of the channel region (“each of the memory cells includes: source and drain regions formed in the substrate and defining a channel region of the substrate extending there between, a floating gate disposed vertically over and insulated from a first portion of the channel region, a select gate disposed vertically over and insulated from a second portion of the channel region,” Claim 1).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the cell structure of Liang in the cited prior art in order to allow for selective erasure of just a portion of a row of memory cell pairs (Paragraph 0012).
Claim 20 is the semiconductor device corresponding to claim 19,and is rejected under similar rationale.
ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Rejections - USC 102/103
On pages 9-10 of the submitted remarks, applicant argues the cited prior art of Yuan in view of Fong fails to teach claims 3 and 11 as amended. This argument has been considered and is persuasive. Thus, the prior rejection has been withdrawn. However, a new rejection has been made as noted above.
On pages 11-12 of the submitted remarks, applicant argues the cited prior art fails to teach all elements of claims 5 and 13.
This argument has been considered but is not persuasive.
Applicant indicates that in the invention, a program pulse is applied “to provide a programming margin above the target program state.” This element is not in the claims. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Applicant further argues “Moschiano teaches that the slower rate of programming is achieved by using a lower program voltage for the program pulse of step 410” according to Paragraph 0032 of Moschiano. The examiner respectfully disagrees, as Paragraph 0032 of Moschiano describes slowing the rate of programming using a bit line bias, further shown on Fig. 5C and described on Paragraph 0043. Fig. 5A shows the program pulses increasing until a maximum voltage level is reached, and therefore the extra program pulse is at least the program voltage with the fixed voltage level, and therefore includes the program voltage with the fixed voltage level.
These arguments apply similarly to claims 6 and 14, argued by applicant on page 12 of the submitted remarks. The examiner further notes that applicant’s argument on page 12 of the submitted remarks that “the extra program pulse has the same program voltage level compared to that of the successive program pulses” is not required in the broadest reasonable interpretation of claims 6 and 14, as claims 6 recites “the extra program pulse includes the program voltage with a voltage level that is the same as a voltage level of the program voltage in a last one of the successive program pulses.” Therefore, if the program voltage with a voltage level that is the same as a voltage level of the program voltage in a last one of the successive program pulses is included in (i.e., at least as large as) the extra pulse, which is shown on Fig. 5A of Moschiano, this claim limitation is met in the broadest reasonable interpretation.
CLOSING COMMENTS
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. ' 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 2-8 and 10-20 have been rejected in the application.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mark Giardino whose telephone number is (571) 270-3565 and can normally be reached on M-F 9:00-5:00- 5:30pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Jared Rutz can be reached on 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
/MARK A GIARDINO JR/Primary Examiner, Art Unit 2135
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