DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement filed 04/17/2025 fails to comply with the provisions of 37 CFR 1.98(a)(4) because it lacks the appropriate size fee assertion. It has been placed in the application file, but the information referred to therein has not been considered as to the merits.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2,10,14, 16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (US 2024/0185799)
As to Claim 1, Park et al. discloses A display panel comprising: a plurality of pixels (fig.1, subpixels SP; para.0037); a plurality of scan lines electrically connected to the plurality of pixels (fig.1, gate lines GL connected to the subpixels SP; para.0037);
a plurality of stages electrically connected to the plurality of scan lines and arranged along a first direction (fig.1, 8-9; gate driving circuit 130 include a plurality of stages ST; para.0072, 0219); and
a plurality of carry lines connected to the plurality of stages (fig.8-9; carry signals C; para.0219)
wherein: the plurality of stages include a first stage (fig.9, stage ST k-1), a second stage (fig.9, ST k) and a third stage (fig.9, ST k+1);
the plurality of carry lines include a first carry line connected to the first stage and the second stage (fig.1, carry signal line C(k-1) connected to first stage ST k-1 and second stage ST k),
a second carry line connected to the first stage, the second stage, and the third stage (fig.9, carry signal line C(k) connected to first stage ST k-1, second stage ST k, and third stage ST k+1), and
a third carry line connected to the second stage and the third stage (fig.9, carry signal line C(k+1) connected to second stage ST k and third stage ST k+1); and
in a region in which the second stage is located, the first carry line and the third carry line do not overlap each other in a second direction intersecting the first direction (fig.9, carry line C(k-1) and carry line C(k-1) do not overlap in region in which stage ST k is located).
As to Claim 2, Park et al. discloses wherein the second carry line (fig.9, second carry line C(k)) comprises a curved portion (fig.9, the curved portion of line C(k) as it is input to first stage ST k-1 and as input to third stage ST k+1), wherein the curved portion overlaps a region between an end of the first carry line and an end of the third carry line (fig.9, curved portion of second carry line C(k) overlaps region between end of first carry C(k-1) {input to stage ST k} and an end of third carry C(k+1) {input to stage ST k}).
As to Claim 10, Park et al. discloses wherein the plurality of pixels comprise Y pixels (Y is an integer of 2 or greater) arranged along the first direction, wherein the second stage outputs scan signals to Y scan lines connected to the Y pixels among the plurality of scan lines (fig.1,9; para.0072; stage ST k output scan signals SOUT corresponding to gate lines connected to subpixels).
As to Claim 14, Park et al. discloses A display panel comprising: a plurality of pixels arranged along a first direction (fig.1, subpixels SP); a plurality of scan lines connected to the plurality of pixels (fig.1, gate lines GL connected to the subpixels SP; para.0037);
a reference stage configured to output a plurality of scan signals to the plurality of scan lines (fig.9, stage ST k, scan lines SOUT; para.0227);
a first peripheral stage spaced apart from the reference stage in the first direction (fig.9, stage ST k-1); a second peripheral stage spaced apart from the first peripheral stage in the first direction with the reference stage interposed therebetween (fig.9, stage ST k+1);
a first peripheral carry line configured to transfer a carry signal output from the first peripheral stage (fig.9, carry signal C(k-1)); and a second peripheral carry line configured to transfer a carry signal output from the second peripheral stage (fig.9, carry signal C(k+1)),
wherein the first peripheral carry line and the second peripheral carry line do not overlap each other in a second direction intersecting the first direction (fig.9, carry signal C(k-1)) and carry signal C(k+1) do not overlap).
As to Claim 16, has limitations similar to those of Claim 2 and are met by the reference as set forth above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 2024/0185799).
As to Claim 3, Park et al. discloses wherein the first stage is an X-1-th stage, the second stage is an X-th stage, and the third stage is an X+1-th stage (fig.9, stages ST k-1, k, k+1).
Park et al. does not expressly disclose wherein the X is an integer of 2 or greater. However, Park et al discloses where k is a natural number greater than or equal to one (fig.9, para.0221,0228). Thus, where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. (MPEP 2144.05.I).
As to Claim 4, Park et al. discloses wherein the first stage is an X-2-th stage, the second stage is an X-th stage, and the third stage is an X+2-th stage (fig.4, stages n-2, n, n+2; fig. 9).
Park et al. does not expressly disclose wherein the X is an integer of 3 or greater. However, Park et al discloses where n (and k) is a natural number greater than or equal to one (fig.9, para.0211, 0221,0228). Thus, where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. (MPEP 2144.05.I).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 2024/0185799) in view of Seo et al. (US 2025/0218395).
As to Claim 8, Park et al. discloses wherein the second stage is electrically connected to four scan lines among the plurality of scan lines (fig.9, para.0227, each stage circuits ST may output a plurality of scan signals SOUT, where the plurality of scan signals SOUT may be four scan signals SOUT).
Park et al. does not expressly disclose connected to six scan lines among the plurality of scan lines. Seo et al. discloses where each stage may output five or more gate signals (para.0089).
The combination of Park et al. in view of Seo et al. each element would have performed the same function as it did separately. Therefore, one of ordinary skill in the art would have
recognized that the results of the combination would yield predictable results, in particular, each stage connected to six scan lines among the plurality of scan lines as claimed.
Claim(s) 9, 12-13, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 2024/0185799) in view of Kim et al. (US 2024/0257765)
As to Claim 9, Park et al. does not expressly disclose, but Kim et al. discloses: wherein each of the plurality of stages comprises a plurality of clock terminals configured to receive a plurality of clock signals (Park-fig.8; para.0082,0314).
Park et al. does not expressly disclose, but Kim et al. discloses wherein: in a first mode driven at a first frequency, the plurality of clock signals have different phases from each other (fig.1,6,9, region A2 - 60Hz, odd clock SCLK-01 and even clock SCLK_E have different phases), and in a second mode driven at a second frequency higher than the first frequency, some clock signals among the plurality of clock signals have a same phase (fig.1,6,9, region A1 driven 120Hz, odd clock SCLK-01, SCLK_02 have the same phase).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Park et al. with the teachings of Kim et al., the motivation being to provide a multi-frequency mode operation in which image quality is improved.
As to Claim 12, Park et al. discloses wherein: the plurality of scan lines comprise a plurality of first scan lines and a plurality of second scan lines (fig.9, scan lines SOUT).
Park et al. does not expressly disclose, but Kim et al. discloses: the plurality of stages include a plurality of first-type stages electrically connected to the plurality of first scan lines (fig.6,9; odd scan stage S(n+1); para.0164,0166, 0197) and a plurality of second-type stages electrically connected to the plurality of second scan lines (fig.6,9; even scan stage, para. 0164,0167, 0202); and the plurality of first-type stages and the plurality of second-type stages are alternately and repeatedly arranged one by one along the first direction (fig.6, odd and even scan stages alternate; odd scan stage S(n+3), even scan stage S(n+4); para.0202-0204).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Park et al. with the teachings of Kim et al., the motivation being to provide a multi-frequency mode operation in which image quality is improved (para.0240-0243).
As to Claim 13, Park et al. in view of Kim et al. disclose wherein each of the plurality of pixels comprises a light emitting element (Kim-fig.3, light emitting diode OD; para.0080), a first transistor (Kim-fig.3, transistor DT), a second transistor (Kim-fig.3, transistor T1), and a third transistor (Kim-fig.3, transistor T6), wherein the first transistor is connected to the light emitting element (Kim-fig.3, transistor DT), the second transistor is connected to a gate electrode of the first transistor (Kim-fig.3, transistor T1 connected to gate of transistor DT), and the third transistor is connected to the light emitting element (Kim-fig.3, transistor T6 connected to OD), wherein an operation of the second transistor is controlled by one corresponding first scan line among the plurality of first scan lines (Kim-fig.3, transistor T1 connected to scan line Sc1) and an operation of the third transistor is controlled by one corresponding second scan line among the plurality of second scan lines (Kim-fig.3, transistor T6 connected to scan line SCn3).
As to Claim 20, Park et al. discloses An electronic device comprising: a plurality of pixels arranged along a first direction (fig.1, subpixels SP); a stage including a plurality of clock terminals configured to control an operation of the plurality of pixels and configured to receive a plurality of clock signals (Park-fig.3,8-9; para.0082,0314; stage ST k): a first carry line configured to transfer a first carry signal to the stage (fig.9, carry signal C(k-1) to stage ST k);
a second carry line configured to transfer a second carry signal generated from the stage (fig.9, carry signal C(k) from stage ST k); and
a third carry line configured to transfer a third carry signal to the stage (fig.9, carry signal C(k+1) to stage ST k), wherein: when viewed in a second direction intersecting the first direction, the first carry line and the third carry line are spaced apart from each other (fig.9, carry signal C(k-1) and C(k+1) are spaced apart).
Park et al. does not expressly disclose, but Kim et al. discloses: in a first mode driven at a first frequency, the plurality of clock signals have different phases from each other (fig.1,6,9, region A2 - 60Hz, odd clock SCLK-01 and even clock SCLK_E have different phases); and in a second mode driven at a second frequency higher than the first frequency, some clock signals among the plurality of clock signals have a same phase (fig.1,6,9, region A1 driven 120Hz, odd clock SCLK-01, SCLK_02 have the same phase).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Park et al. with the teachings of Kim et al., the motivation being to provide a multi-frequency mode operation in which image quality is improved.
Claim(s) 11,15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 2024/0185799) in view of Kim et al. (US 2024/0257765), further in view of Shin et al. (US 2025/0273146).
As to Claim 11, Park et al. does not expressly disclose, but Kim et al. discloses wherein: in a first mode driven at a first frequency, first-mode scan signals output to the Y scan lines have different phases from each other (fig.9, region A2-60 Hz); and in a second mode driven at a second frequency higher than the first frequency, some second-mode scan signals among second-mode scan signals output to the Y scan lines have a same phase as each other (fig.9, region A1-120Hz, scan signals have a same phase).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Park et al. with the teachings of Kim et al., the motivation being to provide a multi-frequency mode operation in which image quality is improved (para.0240-0243).
Park et al. in view of Kim et al., do not expressly disclose where scan lines have different phases from each other.
Shin et al. discloses a scan driver generates a plurality of scan signals having different phases based on gate control signal (para.0037, 0045).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Park et al. in view of Kim et al., with the teachings of Shin et al., to select the pixel row in which data can be written, and reduce luminance deviation when a gray level of an image data is changed.
As to Claim 15 has limitations similar to those of Claim 11 and are met by the references as set forth above.
Allowable Subject Matter
Claim 5-7, 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Claim 5 & 17 is allowable over the prior art of record since the cited references taken alone or in combination do not teach or suggest “ wherein the second carry line comprises a first line portion, a second line portion electrically connected to the first line portion, and a connection portion connected to the first line portion and the second line portion, wherein: the first line portion and the second line portion are on a same layer; and the connection portion is on a different layer from the first line portion and the second line portion” along with the other limitations in the claim.
Conclusion
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/DISMERY MERCEDES/Primary Examiner, Art Unit 2627