DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 10,12,14,16,20 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Kim et al. (US 2024/0029639)
As to Claim 1, Kim et al. discloses A display panel comprising: a plurality of pixels (fig.2-4; pixels P; para.0078); a plurality of scan lines electrically connected to the plurality of pixels (fig.3-4; gate lines GL; para.0114-0115);
a plurality of stages electrically connected to the plurality of scan lines and arranged along a first direction (fig.2-3,7; stage circuit units 1501-150m arranged in vertical direction; para.0088,0091-0092), and
a plurality of carry lines connected to the plurality of stages (fig.6, carry lines CSL including a plurality of carry lines CSL1 and plurality of carry lines CSL2; para.0161),
wherein: the plurality of stages include a first stage (fig.7, stage unit 150n-2), a second stage (fig.7, stage unit 150n), and a third stage (fig.7, stage unit 150n+2);
the plurality of carry lines include a first carry line connected to the first stage and the second stage (fig.7, carry line CSL1 connected to first stage 150n-2 and second stage 150n), a second carry line connected to the first stage, the second stage, and the third stage (fig.7, carry line CSL2 connected to stage 150n, stage 150n-2 and third stage 150n+2 via CSL1), and
a third carry line connected to the second stage and the third stage (fig.7, carry line CSL2 connected to stage 150n+2 and stage 150n);
in a region in which the second stage is located (fig.7, region corresponding to horizontal line Hln), the first carry line and the third carry line are spaced apart from each other in a second direction intersecting the first direction with a qap therebetween (fig.7, carry line CSL1 (connected to stage 150n-2) and carry line CSL2 (connected to stage 150n+2) are spaced apart from each other in horizontal direction); and the second carry line passes through the qap (fig.7, carry line CSL2 connected to stage 150n passes through space between carry line CSL1 (connected to stage 150n-2) and carry line CSL2 (connected to stage 150n+2)).
As to Claim 2, Kim et al. discloses wherein the second carry line comprises a curved portion, wherein the curved portion overlaps a region between an end of the first carry line and an end of the third carry line (fig.7, carry line CSL2 (connected to stage 150n) overlaps region between an end of carry line CSL1 (connected from 150n-2 to stage 150n ) and an end of carry line CSL2 (connected from stage 150n+2 to stage 150n)).
As to Claim 10, Kim et al. discloses wherein the plurality of pixels comprise Y pixels (Y is an integer of 2 or greater) arranged along the first direction, wherein the second stage outputs scan signals to Y scan lines connected to the Y pixels among the plurality of scan lines (fig.2-3, pixels P; para.0087-0088).
As to Claim 12, Kim et al. discloses plurality of scan lines comprise a plurality of first scan lines and a plurality of second scan lines (para.0092- odd numbered gate lines and even numbered gate lines); the plurality of stages include a plurality of first-type stages electrically connected to the plurality of first scan lines (fig.7, odd stage units 150n-2, 150n, 150n+1), and a plurality of second-type stages electrically connected to the plurality of second scan lines (fig.7, even stage units 150n-1, 150n+1); and the plurality of first-type stages and the plurality of second-type stages are alternately and repeatedly arranged one by one along the first direction (fig.7).
As to Claim 14, Kim et al. discloses A display panel comprising: a plurality of pixels arranged along a first direction (fig.2-4; pixels P; para.0078); a plurality of scan lines connected to the plurality of pixels (fig.3-4; gate lines GL; para.0114-0115);
a reference stage configured to output a plurality of scan signals to the plurality of scan lines (fig.7, stage circuit unit 150n; para.059-0161);
a first peripheral stage spaced apart from the reference stage in the first direction (fig.7, stage unit 150-n); a second peripheral stage spaced apart from the first peripheral stage in the first direction with the reference stage interposed therebetween (fig.7, stage unit 150n+2);
a carry line configured to output a carry signal generated from the reference stage (fig.7, carry signal CSL2 from stage unit 150n to stage unit 150n-2); a first peripheral carry line configured to transfer a carry signal output from the first peripheral stage (fig.7, carry signal CSL1 from stage unit 150n-2 to stage 150n); a second peripheral carry line configured to transfer a carry signal output from the second peripheral stage (fig.7, carry signal CSL2 from stage unit 150n+2 to stage unit 150n), wherein the first peripheral carry line and the second peripheral carry line are spaced apart from each other in a second direction intersecting the first direction with a gap therebetween (fig.7, carry line CSL1 (connected to stage 150n-2) and carry line CSL2 (connected to stage 150n+2) are spaced apart from each other in horizontal direction); and the carry line passes through the gap. (fig.7, carry line CSL2 connected to stage 150n passes through space between carry line CSL1 (connected to stage 150n-2) and carry line CSL2 (connected to stage 150n+2).
As to Claim 16, has limitations similar to those of Claim 2 and are met by the reference as set forth above.
As to Claim 20, Kim et al. An electronic device comprising: a plurality of pixels arranged along a first direction (fig.2-4; pixels P; para.0078); a stage including a plurality of clock terminals configured to control an operation of the plurality of pixels and configured to receive a plurality of clock signals (para.0160, plurality of gate control lines may include plurality of shift clock lines, plurality of carry shift clock lines): a first carry line configured to transfer a first carry signal to the stage (fig.7, carry line CSL1 from stage 150n-2 to stage 150n);
a second carry line configured to transfer a second carry signal generated from the stage (fig.7, carry line CSL2 from stage 150n to stage 150n-2 and CSL1 from stage 150n to stage 150n+2); and
a third carry line configured to transfer a third carry signal to the stage (fig.7, carry line CSL2 from stage 150n+2 to stage 150n),
wherein: when viewed in a second direction intersecting the first direction, the first carry line and the third carry line are spaced apart from each other with a gap therebetween (fig.7, carry line CSL1 (connected to stage 150n-2) and carry line CSL2 (connected to stage 150n+2) are spaced apart from each other in horizontal direction); and the second carry line passes through the gap (fig.7, carry line CSL2 connected to stage 150n passes through the space between carry line CSL1 (connected to stage 150n-2) and carry line CSL2 (connected to stage 150n+2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2024/0029639) in view of Park et al. (US 2024/0185799).
As to Claim 3, Kim et al. discloses where the stages 150n-2, 150n, 150n+2, where n may be 2 or more (fig.7, para.0161-0162). Kim et al. does not expressly disclose wherein the first stage is an X-1-th stage, the second stage is an X-th stage, and the third stage is an X+1-th stage, wherein the X is an integer of 2 or greater.
Park et al. wherein the first stage is an X-1-th stage, the second stage is an X-th stage, and the third stage is an X+1-th stage (fig.9, stages STk-1, STk, STk+1, where k may be greater than or equal to one; para.0221,0228).
The combination of Kim et al. in view of Park et al. element would have performed the same function as it did separately. Therefore, one of ordinary skill in the art would have recognized that the results of the combination would yield predictable results, in particular stage configuration as recited in claim 3, as well as the claims that depend therefrom. Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kim et al., with the teachings of Park et al. to provide a gate driving circuit having a small-area structure, thereby reducing the bezel width of the display device.
As to Claim 4, Kim et al. in view of Park et al. discloses wherein the first stage is an X-2-th stage, the second stage is an X-th stage, and the third stage is an X+2-th stage, wherein the X is an integer of 3 or greater (Kim-fig.7, stages 150n-2, 150n, 150n+2; where n may be 2 or more; para.0161-0162; Park-fig.4, 9).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2024/0029639) in view of Seo et al. (US 2025/0218395).
As to Claim 8, Kim et al. does not expressly disclose wherein the second stage is electrically connected to six scan lines among the plurality of scan lines.
Seo et al. discloses a plurality of stages, where each stage may output five or more gate signals (fig. 3, para.0089).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Kim et al. with the teachings of Seo et al, the motivation being to provide a plurality of stage circuits that may output five or more gate signals, thereby reducing the size of the gate driving circuit.
Claim(s) 9, 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2024/0029639) in view of Kim et al. (US 2024/0257765, hereinafter Kim765)
As to Claim 9, Kim et al. does not expressly disclose, but Kim765 discloses: wherein each of the plurality of stages comprises a plurality of clock terminals configured to receive a plurality of clock signals (Kim765-para.0164), wherein: in a first mode driven at a first frequency, the plurality of clock signals have different phases from each other (fig.1,6,9, region A2 - 60Hz, odd clock SCLK-01 and even clock SCLK_E have different phases), and in a second mode driven at a second frequency higher than the first frequency, some clock signals among the plurality of clock signals have a same phase (fig.1,6,9, region A1 driven 120Hz, odd clock SCLK-01, SCLK_02 have the same phase).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kim et al. with the teachings of Kim765, the motivation being to provide a multi-frequency mode operation in which image quality is improved.
As to Claim 13, Kim et al. discloses wherein each of the plurality of pixels comprises a light emitting element (fig.4, light emitting device ED), a first transistor (fig.4, transistor Tdr), a second transistor (fig.4, transistor Tsw1), and a third transistor (fig.4, transistor Tsw2), wherein the first transistor is connected to the light emitting element (fig.4, transistor Tdr connected to ED at node n2), the second transistor is connected to a gate electrode of the first transistor (fig.4, transistor Tsw1 connected to gate of Tdr at node n1), and the third transistor is connected to the light emitting element (fig.4, transistor Tsw2 connected to ED), wherein an operation of the second transistor is controlled by one corresponding first scan line among the plurality of first scan lines (fig.4, gate of transistor Tsw1 connected to gate line GLo) and an operation of the third transistor is controlled by one corresponding second scan line among the plurality of second scan lines.
Kim et al. does not expressly disclose where and an operation of the third transistor is controlled by one corresponding second scan line among the plurality of second scan lines.
Kim765 discloses a pixel circuit comprising a second transistor (Kim765-fig.3, transistor T1), and a third transistor (Kim-fig.3, transistor T6), and wherein an operation of the second transistor is controlled by one corresponding first scan line among the plurality of first scan lines (Kim765-fig.3, transistor T1 connected to scan line Sc1) and an operation of the third transistor is controlled by one corresponding second scan line among the plurality of second scan lines (Kim765-fig.3, transistor T6 connected to scan line SCn3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kim et al. with the teachings of Kim765, the motivation being to provide to provide scan signal that can be used for compensation and a scan signal that can be used for initialization, thereby providing compensation for threshold voltage of the driving transistor and initialization of the light emitting device.
Claim(s) 11, 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2024/0029639) in view of Kim et al. (US 2024/0257765, hereinafter Kim765), further in view of Shin et al. (US 2025/0273146).
As to Claim 11, Kim et al. does not expressly disclose, but Kim765 discloses wherein: in a first mode driven at a first frequency, first-mode scan signals output to the Y scan lines have different phases from each other (fig.9, region A2-60 Hz); and in a second mode driven at a second frequency higher than the first frequency, some second-mode scan signals among second-mode scan signals output to the Y scan lines have a same phase as each other (fig.9, region A1-120Hz, scan signals have a same phase).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kim et al. with the teachings of Kim765, the motivation being to provide a multi-frequency mode operation in which image quality is improved (para.0240-0243).
Kim et al. in view of Kim765 do not expressly disclose where in the first mode, scan lines have different phases from each other.
Shin et al. discloses a scan driver generates a plurality of scan signals having different phases based on gate control signal (para.0037, 0045).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Kim et al. in view of Kim765, with the teachings of Shin et al., the motivation being to select the pixel row in which data can be written, and reduce luminance deviation when a gray level of an image data is changed.
As to Claim 15 has limitations similar to those of Claim 11 and are met by the references as set forth above.
Allowable Subject Matter
Claims 5-7, 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1,14,20 have been considered but are moot because the new ground of rejection applied as necessitated by amendment.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DISMERY E. MERCEDES whose telephone number is (571)272-7558. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
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/DISMERY MERCEDES/Primary Examiner, Art Unit 2627
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