DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-18 of U.S. Patent No. . 12,332,810. Although the claims at issue are not identical, they are not patentably distinct from each other as demonstrated by the example mapping of the claims below.
Patent No. 12,332,810 (Claim 1)
Application (Claim1)
(Claim 1) An electronic device, comprising: a first chiplet comprising a first bus interface, a first interconnect management module, and a first interconnect module; and a second chiplet connected to the first chiplet through the first interconnect module,
(Claim 1) An electronic device, comprising: a first chiplet comprising a first bus interface, a first interconnect management module, and a first interconnect module; anda second chiplet connected to the first chiplet through the first interconnect module,
(Claim 1) wherein, in response to an occurrence of a request transaction associated with the second chiplet, the first interconnect management module stores first information associated with the request transaction in a register,
(Claim 1) wherein, in response to an occurrence of a request transaction associated with the second chiplet, the first interconnect management module stores first information, associated with the request transaction, in a first register,
(Claim 3) the request transaction is transferred to the second chiplet through the first interconnect module.
(Claim 1) the request transaction is transferred to the second chiplet through the first interconnect module,
(Claim 6) the second chiplet includes a second bus interface, a second interconnect management module, and a second interconnect module
(Claim 1) the second chiplet includes a second bus interface, a second interconnect management module, and a second interconnect module,
(Claim 6) in response to the occurrence of the request transaction, the second interconnect management module stores, in a register, second information associated with the request transaction
(Claim 1) in response to the occurrence of the request transaction, the second interconnect management module stores, in a second register, second information associated with the request transaction,
(Claim 1) wherein the first information comprises information associated with a first time of occurrence of the request transaction in the first interconnect management module, and
(Claim 1) the second information includes information associated with a first time of occurrence of the request transaction in the second interconnect management module,
(Claim 1) the first interconnect management module determines occurrence or non-occurrence of a request transaction timeout in the first chiplet, based on whether a transfer of the request transaction is completed before a first threshold time elapses since the first time, and
(Claim 1) the second interconnect management module determines occurrence or non-occurrence of a request transaction timeout in the second chiplet, based on whether a transfer of the request transaction is completed before a first threshold time elapses since the first time, and
(Claim 1) in response to determining that the request transaction timeout occurs in the first chiplet, the first bus interface is determined as a debugging point candidate.
(Claim 1) in response to determining the occurrence of the request transaction timeout in the second chiplet, the second interconnect module is determined as a debugging point candidate.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 15 is rejected under 35 U.S.C. 112(b), as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claim 15, because of the drafting, the claim is ambiguous as to whether the limitations "the transaction" in lines 5-6 is associated with the previous limitation “the timed-out transaction” of claim 15 or the “request transaction” of claim 1; therefore, the scope of the claim is indefinite.
Allowable Subject Matter
As claims 1-20 are rejected on the ground of nonstatutory double patenting and claim 15 is rejected under 35 U.S.C. 112(b), the claims would be allowable if a terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) were filed to overcome the rejection based on nonstatutory double patenting and claim 15 was rewritten to overcome the rejection under 35. U.S.C. 112(b).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The IEEE paper An Embedded Tracing Debug Implementation for Crossbar Type Bus in Multi-core SoC by Duan et al., the IEEE paper Debug Support Strategy for Systems-on-Chips with Multiple Processor Cores by Hopkins et al., the WIPO Publication WO 2024/218022 of Delsing et al., the US Pub. No. 2024/0241811 of Goyal et al., and the US Pub. No. 2024/0329129 of Mathrasanallur et al. are related to chiplet package architecture, testing, and debugging.
The examiner has cited particular column, line, and/or paragraph numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in its entirety as potentially teaching of all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111(c).
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(11) and Interview Practice for additional details.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC T OBERLY whose telephone number is (571)272-6991. The examiner can normally be reached on M-F 800am-430pm (MT).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on (571) 272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC T OBERLY/ Primary Examiner, Art Unit 2184
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