DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/02/2025 is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Claims 1-13, 15-17 and 19-20 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-5, 7-8, 12-18 and 20-21of US. Patent No. 12,300,133. Although the conflicting claims are not identical, they are not patentably distinct from each other because the broader claim limitation of claim 1 of the current application is met by the narrower claim limitation of claim 1 of US. Patent No. 12,300,133 as shown in the following tables and the discussion thereafter.
Current Application
US. Patent No. 12,300,133
1. (Original) A display panel, wherein the display panel comprises an active area and a border- frame area located at a periphery of the active area, the active area comprises a plurality of sub- pixels and a plurality of data lines connected to the sub-pixels, and the border-frame area comprises a testing area and a bonding area;
the testing area comprises a plurality of testing units that are arranged periodically in a first direction, each of the testing units comprises one or more switching transistors, a first electrode of each of the switching transistors is connected to a testing-signal lead wire, the testing-signal lead wire is configured to transmit a testing signal, and a second electrode of the switching transistor is connected to one of the data lines;
the bonding area comprises a plurality of bonding units that are arranged periodically in the first direction, each of the bonding units comprises one or more bonding pads, and each of the bonding pads is connected to one of the data lines;
wherein the border-frame area further comprises an inputting area,
the inputting area comprises a plurality of testing-signal bus lines, and an extending direction of the testing-signal bus lines intersects with an extending direction of the testing-signal lead wires; and
8. (Original) The display panel according to claim 1, wherein the plurality of testing-signal bus lines comprise at least one internal transmission bus, and the internal transmission bus is located at a first metal layer;
the testing-signal lead wires are located at a second metal layer, and a first insulating layer is disposed between the first metal layer and the second metal layer;
a second insulating layer is disposed on one side of the second metal layer that is back away from the first metal layer, a first electrode layer is disposed on one side of the second insulating layer that is back away from the first metal layer, and the first electrode layer comprises a plurality of instances of the switching electrodes; or a third insulating layer is disposed on one side of the first metal layer that is back away from the second metal layer, a second electrode layer is disposed on one side of the third insulating layer that is back away from the second metal layer, and the second electrode layer comprises a plurality of instances of the switching electrodes
the testing-signal bus lines are connected to the testing-signal lead wires;
wherein the testing-signal lead wires and the testing-signal bus lines are connected by switching electrodes; and
a first part of each of the switching electrodes is connected to one of the testing-signal lead wires by a first via hole, and a second part of the switching electrode is connected to one of the testing-signal bus lines by a second via hole.
1. (Currently amended) A display panel, wherein the display panel comprises an active area and a border-frame area located at a periphery of the active area, the active area comprises a plurality of sub-pixels and a plurality of data lines connected to the sub-pixels, and the border- frame area comprises a testing area and a bonding area;
the testing area comprises a plurality of testing units that are arranged periodically in a first direction, each of the testing units comprises one or more switching transistors, a first electrode of each of the switching transistors is connected to a testing-signal lead wire, the testing-signal lead wire is configured to transmit a testing signal, and a second electrode of the switching transistor 1s connected to one of the data lines;
the bonding area comprises a plurality of bonding units that are arranged periodically in the first direction, each of the bonding units comprises one or more bonding pads, and each of the bonding pads is connected to one of the data lines; and
in the first direction, a ratio of a quantity of the switching transistors comprised in one arrangement period of the testing units to a quantity of the bonding pads comprised in one arrangement period of the bonding units is greater than 0 and less than 2;
wherein the border-frame area further comprises an inputting area, the inputting area is located on one side of the testing area that is away from the active area, the inputting area comprises a plurality of testing-signal bus lines, and an extending direction of the testing-signal bus lines intersects with an extending direction of the testing-signal lead wires; and
the testing-signal bus lines are connected to the testing-signal lead wires, and the testing- signal bus lines are configured to input a testing signal via the testing-signal lead wires to data lines of sub-pixels of a same color;
wherein the plurality of testing-signal bus lines comprise at least one internal transmission bus, and the internal transmission bus is located at a first metal layer:
the testing-signal lead wires are located at a second metal layer, and a first insulating layer is disposed between the first metal layer and the second metal layer;
a second insulating layer is disposed on one side of the second metal layer that is back away from the first metal layer, a first electrode layer is disposed on one side of the second insulating layer that is back away from the first metal layer, and the first electrode layer comprises a plurality of switching electrodes: or a third insulating layer is disposed on one side of the first metal layer that is back away from the second metal layer, a second electrode layer is disposed on one side of the third insulating layer that is back away from the second metal layer, and the second electrode layer comprises a plurality of switching electrodes:
the testing-signal lead wires and the internal transmission bus are connected by the switching electrodes; and
a first part of each of the switching electrodes is connected to one of the testing-signal lead wires by a first via hole, and a second part of the switching electrode is connected to the internal transmission bus by a second via hole.
Claim 2 of the present application corresponds to claim 2 of US. Patent No. 12,300,133.
Claim 3 of the present application corresponds to claim 3 of US. Patent No. 12,300,133.
Claim 4 of the present application corresponds to claim 4 of US. Patent No. 12,300,133.
Claim 5 of the present application corresponds to claim 5 of US. Patent No. 12,300,133.
Claim 6 of the present application corresponds to claim 7 of US. Patent No. 12,300,133.
Claim 7 of the present application corresponds to claim 8 of US. Patent No. 12,300,133.
Claim 9 of the present application corresponds to claim 12 of US. Patent No. 12,300,133.
Claim 10 of the present application corresponds to claim 13 of US. Patent No. 12,300,133.
Claim 11 of the present application corresponds to claim 14 of US. Patent No. 12,300,133.
Claim 12 of the present application corresponds to claim 15 of US. Patent No. 12,300,133.
Claim 13 of the present application corresponds to claim 16 of US. Patent No. 12,300,133.
Claim 15 of the present application corresponds to claim 17 of US. Patent No. 12,300,133.
Claim 16 of the present application corresponds to claim 18 of US. Patent No. 12,300,133.
Claim 17 of the present application corresponds to claim 13 of US. Patent No. 12,300,133.
Claim 19 of the present application corresponds to claim 20 of US. Patent No. 12,300,133.
Claim 20 of the present application corresponds to claim 21 of US. Patent No. 12,300,133.
Allowable Subject Matter
Claims 14 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 1-13, 15-17 and 19-20 would be allowed if a Terminal Disclaimer is filed to overcome the Double Patenting rejection(s) set forth in this Office Action.
The following is an examiner’s statement of reasons for allowance:
None of the prior art, made of record, singularly or in combination, teaches or fairly suggests the features presented in the combined limitations of independent claim 1, specifically the limitation stated as “wherein the testing-signal lead wires and the testing-signal bus lines are connected by switching electrodes; and a first part of each of the switching electrodes is connected to one of the testing-signal lead wires by a first via hole, and a second part of the switching electrode is connected to one of the testing-signal bus lines by a second via hole”. The dependent claims 2-20 are allowed for at least the same reason indicated above.
Kwak (US. Pub. No. 2016/0260367) is considered the closest prior art. Kwak discloses a display panel where the display panel comprises an active area located at a peripheral of the active area, the active area comprises a plurality of sub-pixels connected to the sub-pixels. Kwak further discloses the testing area; the bonding area; however, Kim fails to disclose wherein the testing-signal lead wires and the testing-signal bus lines are connected by switching electrodes; and a first part of each of the switching electrodes is connected to one of the testing-signal lead wires by a first via hole, and a second part of the switching electrode is connected to one of the testing-signal bus lines by a second via hole required for claim 1.
Jeon (US. Pub. No. 2007/0018680) discloses a display panel comprising a bonding area, wherein the bonding area is located between an active area and a testing area; however, Jeon fails to disclose wherein the testing-signal lead wires and the testing-signal bus lines are connected by switching electrodes; and a first part of each of the switching electrodes is connected to one of the testing-signal lead wires by a first via hole, and a second part of the switching electrode is connected to one of the testing-signal bus lines by a second via hole required for claim 1.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US. Pub. No. 2022/0336547 (Zhou et al.) is considered as pertinent art as seen in figure 1.
US. Pub. No. 2003/0030464 (Tomita et al.) is also considered as pertinent art as seen in figure 3.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NAN-YING YANG whose telephone number is (571)272-2211. The examiner can normally be reached Monday-Friday, 8am-5pm, EST.
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/NAN-YING YANG/ Primary Examiner, Art Unit 2629