DETAIL ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. The instant application having application No. 19/184,558 has a total of 20 claims pending in the application; there are 3 independent claim and 17 dependent claims, all of which are ready for examination by the examiner.
INFORMATION CONCERNING IDS:
3. The information disclosure statement (IDS) submitted on 04/21/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the Examiner and a copy (copies) of PTOL-1449(s) initiated and signed by the Examiner is/are attached.
INFORMATION CONCERNING DRAWING:
4. The applicant’s drawings submitted on 04/21/2025 are acceptable for examination purposes.
INFORMATION CONCERNING FOREIGN PRIORITY:
5. Acknowledgment is made of applicant’s claim for foreign priority based on an application fled in People’s Republic of China on 11/19/2024.
RELEVANT PRIOR ART THE EXAMINER:
6. The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c).
Zhou (US 20230013322 A1) teaches “…in the SSD that supports a zoned namespace (NS), one namespace is divided into a plurality of zones, and a storage space corresponding to one zone is the first storage space...” (par. 0016).
ESAKA et al. (US 20210223962 A1) teaches “…where the shared flash buffer 201 is realized as the SLC buffer 401 as shown in FIG. 5, the SLC mode is used as the second write mode applied to the shared flash buffer 201. The SLC mode is a write mode in which data written...” (par. 0065).
Kannan et al. (US 20210173588 A1) teaches “… the logical address space of a namespace is divided into zones. Each zone provides a logical block address range that must be written sequentially and explicitly reset before rewriting, thereby enabling the creation of namespaces that expose the natural boundaries of the device and offload management of internal mapping tables to the host. In order to implement NVMe Zoned Name Spaces (‘ZNS’), ZNS SSDs or some other form of zoned block devices may be utilized that expose a namespace logical address space using zones.r…” (par. 217).
INFORMATION CONCERNING CLAIMS:
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. “Lee” (US 2022/0156008 A1) in view of CHOI et al. “Choi” (US/2024/0070067 A1).
7. Regarding claim 1, Lee teaches or suggests:
“A zoned universal flash storage (ZUFS) memory system (e.g., ¶ 0132, Referring additionally to FIGS. 10 to 13, the logical address ADDR_L that may be controlled by the file system 121 may be implemented as one or a plurality of namespaces NS or the like, comprising: a memory device (e.g., Fig. 2 ¶ 0063, storage device 10 may include a memory controller 200, a buffer memory 202, and/or an NVM 300); and a memory controller coupled with the memory device and configured to control the memory device to perform partition storage by zones (e.g., Fig. 2 ¶ 0064, The memory controller 200 may control the operations of the NVM 300 through a channel CH. The memory controller 200 may receive the write command WCMD and the logical address ADDR_L from the host device 100, and write the data to the NVM 300. A detailed description of the logical address ADDR_L according to some example embodiments of the present disclosure will be given below in the description of FIG. 10; Figs. 10-12, ¶ 0133, logical address ADDR_L may include a plurality of zones Z0 to Z15. The file system 121 may program the NVM 300 through the plurality of zones Z0 to Z15. The number of zones included in the logical address ADDR_L, which is illustrated in this drawing). Fig. 10 shows that logical address (ADDR_L) comprises (e.g., divided or partitioned into a plurality of zones (e.g., zones Z0 to Z15) and each zone is associated with a memory block (e.g., BLK 0 to BLK 15 in NVM 300. Fig. 10 also shows zones are associated with a plurality of different memory cell types or modes (e.g., Z0-Z3 with SLC, Z4-Z7 with MCL, Z8-Z11 with TLC, Z12-Z15 with QCL), see also Fig. 12.
wherein a storage space of a zone is configured to support sequential writing (e.g., ¶ 0159, the write operation may be performed in a sequential write manner), wherein the memory controller is configured with a first interface for coupling with a host (e.g., Fig. 9 shows that memory controller coupled to the host to receive commands and to the NVM to transmit the commands), and receives a first command from the host through the first interface (e.g., ¶ 0130, FIGS. 2, 8, and 9, the host device 100 may send the write mode command WMCMD to the memory controller 200 (S110), the first command comprises specified mode information (e.g., 0130), and the specified mode information indicates a storage mode of a to-be-created zone (e.g., ¶ 0139, the 0th to third memory blocks BLK 0 to BLK 3 store write mode data corresponding to a single-level cell (SLC) write mode). Fig. 2 shows memory controller 200 is coupled to the host controller 130 and received the write command write command from the host controller. However, Lee does not appear to expressly teach while Choi discloses:
“and the memory controller is further configured to: determine whether available storage space of the memory device satisfies a creation condition according to the specified mode information;” (e.g., Fig. 12, ¶¶ 0208-0214). At operation S510, the memory controller receive a write request for a zone (1st type). At S520, the zone type or request is checked, if it is of first type the memory controller at S530 check to determine whether the number of erased unit (e.g., EU) is greater than a third threshold TH3. If it is, opens (e.g., create -success) a zone of 1st type at S540. At S530, if number free EU is not greater TH3 (e.g., it is less than or equal to TH3), 1st type zone is not created (e.g., a failure). At S550 a zone of second type is being generated. At S560 the result of operation (e.g., success or failure) is transmitted to the host device.
“and create a zone with the storage mode according to the first command in response to the available storage space satisfying the creation condition.” (e.g., Fig. 12, ¶ 0211, When the number of free erase units EU is greater than the third threshold value TH3, in operation S540, the memory controller 120 may open a zone having a first type (e.g., a reserved zone). The memory controller 120 may allocate erase units of an area, which is dedicated such that the reserved zone is generated, to the reserved zone. The first-type zone may have a cell type lower than the cell type of the target zone. The first-type zone may have the SLC cell type
Disclosures by Lee and Choi are analogous because they are in the same field of endeavor and/or solving a similar or common problem.
It would have been obvious to a person of having ordinary skill in the art before the effective filing date of the claimed invention to modify the storage device comprising memory blocks of different types taught by Lee to determine free or available space (e.g., number erased or free blocks) satisfies a creation condition (e.g., > 3th threshold) comprising the write mode indicated in the command.
The motivation for including the power mode change request as taught by paragraph [0152] of Choi is to improve write speed of memory device.
Therefore, it would have been obvious to combine teaching of Choi with Lee to obtain the invention as specified in the claim.
10. The independent claims 10 and 19 are system claim and method claim versions of the independent claim 1. They include similar limitations as the independent claim 1 and are rejected based on the same ground of rejection presented above with respect to claim 1.
8. Regarding claims 2, 11, and 20, Choi further teaches:
“wherein the memory controller is configured to: set a state of the created zone to an open state;” (e.g., Fig. 12, ¶ 0211, the memory controller 120 may open a zone having a first type”
“and send creation success information to the host through the first interface.” (e.g., Fig. 12, ¶ 0214, In operation S560, the memory controller 120 may transmit a response including a zone type to the external host device. For example, when there is opened a zone of a type different from the type of the zone requested by the external host device, the response may include information about the opened zone. When the opened zone has the type requested by the external host device).
9. Regarding claims 3 and 12, Choi further teaches:
“wherein the memory controller is configured to in response to the available storage space not satisfying the creation condition, send creation failure information to the host through the first interface.” (e.g., Fig. 12, ¶¶ 0208-0214). If the write request is a first type of request (e.g., step 520, yes) and the number of free FU is not greater or equal to a third threshold TH3 (e.g., step 530, no), the first type zone cannot be generated (e.g., failure). The result of operation is transmitted to the host (e.g., response S560).
10. Regarding claim 5 Choi further teaches:
“wherein the memory controller is further configured to: receive a zone writing request and writing data through the first interface;” (e.g., Fig. 12, ¶ 0208, in operation S510, the memory controller 120 of the storage device 100 may receive the open zone request OZ or the write request WR from the external host device)
“and write the writing data into the created zone according to the zone writing request.” (e.g., Fig. 12, ¶ 0211, in operation S540…The first-type zone may have the SLC cell type. The memory controller 120 may permit random writes with respect to the zone having the first type).
11. Regarding claims 6 and 14, Lee further teaches:
“wherein the storage mode comprises a first storage mode and a second storage mode, each of memory cells corresponding to the storage space of the zone configured with the first storage mode is capable of being written with N bits of data; each of the memory cells corresponding to the storage space of the zone configured with the second storage mode is capable of being written with M bits of data, M and N are integers greater than or equal to 1, and M is greater than N.” (e.g., Fig. 12, ¶ 0143, Z0 stores 0th data D0 of the 0th zone Z0 according to the SLC write mode, the fourth memory block BLK 4 corresponding to the fourth zone Z4 stores fourth data D4 of the fourth zone Z4 according to the MLC). For example, MLC is multi-level cell storing two or more bits per memory cell. MLC is single-level cell storing two one bit per memory cell. Number bits in MLC memory is greater than number bit in SLC memory cell.
12. Regarding claims 7 and 15-16, taking claim 7 as explanatory, Lee further teaches:
“wherein the memory controller is further configured to: receive the zone writing request and writing data through the first interface, wherein the storage mode is the first storage mode responsive to the writing data being hot data, and the storage mode is the second storage mode responsive to the writing data being non-hot data; and write the writing data into the zone created according to the first command according to the zone writing request.” (e.g., Fig. 2, ¶ 0061, host controller 130 may convert a data format of commands (e.g., the write command WCMD and/or a write mode command WMCMD) corresponding to various access requests issued by the host device 100; ¶ 0064, memory controller 200 may determine an operation mode, e.g. a write mode, for the logical address ADDR_L transmitted from the host in response to the write mode command WMCMD; (e.g., Fig. 19, ¶ 0178, the frequency of use of the 0th data D0 in the 0th zone Z0 is high (Hot)… the file system 121 of the host device 100 may set such that a write operation of the 0th memory block BLK 0 is performed according to an SLC write mode or an MLC write mode… When the frequency of use of the 0th data D0 in the 0th zone Z0 is medium (Warm), the file system 121 of the host device 100 may set such that the write operation of the 0th memory block BLK 0 is performed according to an MLC write mode or a TLC write mode…data D0 in the 0th zone Z0 is low (Cold),… the write operation of the 0th memory block BLK 0 is performed according to a TLC write mode or a QLC write mode
13. Regarding claims 9 and 18, Lee further teaches:
“wherein the zone is a zone in a zone namespace (ZNS).” (e.g., ¶ 0132, FIGS. 10 to 13, the logical address ADDR_L that may be controlled by the file system 121 may be implemented as one or a plurality of namespaces NS; ¶ 0133, logical address ADDR_L may include a plurality of zones Z0 to Z15).
Allowable Subject Matter
14. Claims 4, 8, 13, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Direction OF FUTURE CORRESPONDENCES:
15. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HASHEM FARROKH whose telephone number is (571)272-4193. The examiner can normally be reached Monday through Friday from 8:30 am - 5:00 pm.
16. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Mr. Tim Vo can be reached on (571)272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HASHEM FARROKH/Primary Examiner, Art Unit 2138
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