DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 11, and 20 have been amended as per Applicant’s amendment filed on June 1, 2026. No claims have been canceled. Claims 1-20 are pending.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 1 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of copending Application No. 19/182323 (reference application) in view of Yoon (US 2018/0005576 A1, Published January 4, 2018) and Luis (US 2018/0062105 A1, Published March 1, 2018).
Present Application
US Application 19/182323
1. A sub-pixel comprising:
a first transistor having a first electrode connected via a first node to a first power supply voltage node configured to receive a first power supply voltage, a second electrode connected to a second node, and a gate electrode connected to a third node;
a light emitting element connected between the second node and a second power supply voltage node configured to receive a second power supply voltage;
a second transistor connected between a data line and the third node, and having a gate electrode which is connected to a first sub-gate line;
a first capacitor including a first electrode and a second electrode, wherein the first electrode is connected to the third node and the second electrode is connected to the first node;
a second capacitor including a first electrode and a second electrode, wherein the first electrode is connected to the third node and the second electrode is connected to an initialization voltage node configured to receive an initialization voltage; and
a third capacitor including a first electrode and a second electrode, wherein the first electrode is connected to the third node and the second electrode is connected to the second node
wherein the third is commonly connected to the first transistor, a first electrode of the first capacitor, a first electrode of the second capacitor, and a first electrode of the third capacitor, and
wherein the initialization voltage is different from the second power supply voltage.
1. A sub-pixel comprising:
a first transistor having a first electrode connected to a first power supply voltage node configured to receive a first power supply voltage via a first node, a second electrode connected to a second node, and a gate electrode connected to a third node;
a light-emitting element connected between the second node and a second power supply voltage node configured to receive a second power supply voltage;
a second transistor connected between a data line and the third node and having a gate electrode connected to a first sub-gate line;
a first capacitor connected between the first node and the third node;
a second capacitor connected between the third node and a voltage control line; and
a third capacitor connected between the third node and the second node.
2. The sub-pixel of claim 1, wherein the voltage control line is configured to have a low-level voltage based on a data signal from the data line being supplied to the third node and to have a high-level voltage higher than the low-level voltage based on the data signal not being supplied to the third node.
3. The sub-pixel of claim 1, further comprising: a third transistor connected between the first power supply voltage node and the first node and having a gate electrode connected to an emission control line; and a fourth transistor connected between the second node and an initialization voltage node configured to receive an initialization voltage and having a gate electrode connected to a second sub-gate line.
4. The sub-pixel of claim 3, wherein the voltage control line is configured to have a low-level voltage during a period in which the fourth transistor is turned on and to have a high-level voltage higher than the low-level voltage during a period in which the fourth transistor is turned off.
5. The sub-pixel of claim 4, wherein the second transistor is configured to be turned on during a part of a period in which the fourth transistor is turned on.
6. The sub-pixel of claim 3, wherein the first transistor, the second transistor, and the third transistor are P-type transistors, and the fourth transistor is an N-type transistor.
7. The sub-pixel of claim 6, wherein each of the first transistor to the fourth transistor includes a body electrode, and the body electrode of each of the first transistor to the third transistor is configured to receive the first power supply voltage, and the body electrode of the fourth transistor is configured to receive the initialization voltage.
8. The sub-pixel of claim 6, wherein each of the first transistor to the fourth transistor includes a body electrode, and the body electrode of each of the first transistor to the third transistor is configured to receive the first power supply voltage, and the body electrode of the fourth transistor is configured to receive a ground voltage.
9. The sub-pixel of claim 3, wherein one horizontal period is divided into a first period, a second period, and a third period, the second transistor is configured to be turned on during the first period and the second period, the fourth transistor is configured to be turned on during the first period to the third period, the third transistor is configured to be turned off during the second period, and the voltage control line has a low-level voltage during the first period to the third period and has a high-level voltage higher than the low-level voltage during other periods.
10. The sub-pixel of claim 9, wherein the data line is configured to receive a data signal during the first period to the third period.
11. The sub-pixel of claim 9, wherein the third transistor is further configured to be turned off during the first period.
12. A display device comprising: a sub-pixel connected to data lines, gate lines, and emission control lines; a gate driver configured to drive the gate lines and the emission control lines; and a data driver configured to drive the data lines, wherein each of the sub-pixels comprises: a first transistor having a first electrode connected to a first power supply voltage node configured to receive a first power supply voltage via a first node, a second electrode connected to a second node, and a gate electrode connected to a third node; a light-emitting element connected between the second node and the second power supply voltage node configured to receive a second power supply voltage; a second transistor connected between a data line, which is one of the data lines, and the third node and having a gate electrode connected to a first sub-gate line, which is one of the gate lines; a first capacitor connected between the first node and the third node; a second capacitor connected between the third node and a voltage control line, which is one of the gate lines; and a third capacitor connected between the third node and the second node.
13. The display device of claim 12, wherein each of the sub-pixels further comprises: a third transistor connected between the first power supply voltage node and the first node and having a gate electrode connected to an emission control line which is one of the emission control lines; and a fourth transistor connected between the second node and an initialization voltage node configured to receive an initialization voltage and having a gate electrode connected to a second sub-gate line which is one of the gate lines.
14. The display device of claim 13, wherein the first transistor, the second transistor, and the third transistor are P-type transistors, and the fourth transistor is an N-type transistor.
15. The display device of claim 14, wherein each of the first to fourth transistors includes a body electrode, and the body electrode of each of the first to third transistors is configured to receive the first power supply voltage, and the body electrode of the fourth transistor is configured to receive one of the initialization voltage and a ground voltage.
16. The display device of claim 15, wherein one horizontal period is divided into a first period, a second period, and a third period, and the gate driver is configured to: supply a first scan signal having a gate-on voltage to the first sub-gate line during the first period and the second period; supply a second scan signal having a gate-on voltage to the second sub-gate line during the first period to the third period; supply a low-level voltage to the voltage control line during the first period to the third period; and supply an emission control signal having a gate-off voltage to the emission control line during the second period.
17. The display device of claim 16, wherein the gate driver is configured to supply a high-level voltage higher than the low-level voltage to the voltage control line during a period other than the first period to the third period.
18. The display device of claim 16, wherein the gate driver further is configured to supply the emission control signal to the emission control line during the first period.
19. The display device of claim 16, wherein the data driver is configured to supply a data signal to the data line during the first period to the third period.
20. An electronic device, comprising a processor to provide image data; a display device to display an image based on the image data; and wherein the display device, comprising: a sub-pixel connected to data lines, gate lines, and emission control lines; a gate driver configured to drive the gate lines and the emission control lines; and a data driver configured to drive the data lines, wherein each of the sub-pixels comprises: a first transistor having a first electrode connected to a first power supply voltage node configured to receive a first power supply voltage via a first node, a second electrode connected to a second node, and a gate electrode connected to a third node; a light-emitting element connected between the second node and the second power supply voltage node configured to receive a second power supply voltage; a second transistor connected between a data line, which is one of the data lines, and the third node and having a gate electrode connected to a first sub-gate line, which is one of the gate lines; a first capacitor connected between the first node and the third node; a second capacitor connected between the third node and a voltage control line, which is one of the gate lines; and a third capacitor connected between the third node and the second node.
.3. The sub-pixel of claim 2, further comprising: a fourth transistor connected between the second node and the initialization voltage node, and having a gate electrode connected to a second sub-gate line.
4. The sub-pixel of claim 3, wherein the first transistor, the second transistor and the third transistor are P-type transistors, and the fourth transistor is an N-type transistor.
5. The sub-pixel of claim 4, wherein each of the first to fourth transistors includes a body electrode, and the body electrode of each of the first to third transistors are configured to receive the first power supply voltage, and the body electrode of the fourth transistor is configured to receive the initialization voltage.
6. The sub-pixel of claim 3, wherein one horizontal period is divided into a first period, a second period, and a third period, the second transistor is turned on during the first period and the second period, the fourth transistor is turned on during the first period to the third periods, and the third transistor is turned off during the second period.
7. The sub-pixel of claim 6, wherein the data line is configured to receive a voltage of a data signal during the first period to the third period.
8. The sub-pixel of claim 6, wherein the third transistor is configured to be turned off during the first period.
9. The sub-pixel of claim 3, wherein the initialization voltage is a voltage by which the light emitting element is configured to be turned off based on the voltage being supplied to the light emitting element.
10. The sub-pixel of claim 2, further comprising: a fourth transistor connected between the second node and an auxiliary initialization voltage node configured to receive an auxiliary initialization voltage, and having a gate electrode connected to a second sub-gate line, wherein the auxiliary initialization voltage is a voltage which is different from the initialization voltage.
11. A display device comprising: sub-pixels connected to data lines, gate lines, and emission control lines; a gate driver configured to drive the gate lines and the emission control lines; and a data driver configured to drive the data lines, each of the sub-pixels comprising: a first transistor having a first electrode connected via a first node to a first power supply voltage node configured to receive a first power supply voltage, a second electrode connected to a second node, and a gate electrode connected to a third node; a light emitting element connected between the second node and a second power supply voltage node configured to receive a second power supply voltage; a second transistor connected between a data line which is any one of the data lines and the third node, and having a gate electrode connected to a first sub-gate line which is any one of the gate lines; a first capacitor connected between the first node and the third node; a second capacitor connected between an initialization voltage node to which an initialization voltage is inputted and the third node; and a third capacitor connected between the third node and the second node.
12. The display device of claim 11, wherein each of the sub-pixels further comprises a third transistor connected between the first power supply voltage node and the first node and having a gate electrode connected to an emission control line which is any one of the emission control lines.
13. The display device of claim 12, wherein each of the sub-pixels further comprises a fourth transistor connected between the second node and the initialization voltage node and having a gate electrode which is connected to a second sub-gate line which is any one of the gate lines.
14. The display device of claim 13, wherein the first transistor, the second transistor and the third transistor are P-type transistors, and the fourth transistor is an N-type transistor.
15. The display device of claim 14, wherein each of the first to fourth transistors includes a body electrode, and the body electrode of each of the first to third transistors are configured to receive the first power supply voltage, and the body electrode of the fourth transistor is configured to receive the initialization voltage.
16. The display device of claim 13, wherein one horizontal period is divided into a first period, a second period, and a third period, and the gate driver is configured to supply a first scan signal with a gate-on voltage to the first sub-gate line during the first period and the second period, to supply a second scan signal with a gate-on voltage to the second sub-gate line during the first period to the third period, and to supply an emission control signal with a gate-off voltage to the emission control line during the second period.
17. The display device of claim 16, wherein the data driver is configured to supply a voltage of a data signal to the data line during the first period to the third period.
18. The display device of claim 16, wherein the gate driver is further configured to supply the emission control signal to the emission control line during the first period.
19. The display device of claim 12, wherein each of the sub-pixels further comprises a fourth transistor connected between the second node and an auxiliary initialization voltage node to which an auxiliary initialization voltage is supplied and having a gate electrode which is connected to a second sub-gate line which is any one of the gate lines, and the auxiliary initialization voltage is a voltage which is different from the initialization voltage.
20. An electronic device, comprising a processor to provide image data; a display device to display an image based on the image data; and wherein the display device, comprising: sub-pixels connected to data lines, gate lines, and emission control lines; a gate driver configured to drive the gate lines and the emission control lines; and a data driver configured to drive the data lines, each of the sub-pixels comprising: a first transistor having a first electrode connected via a first node to a first power supply voltage node configured to receive a first power supply voltage, a second electrode connected to a second node, and a gate electrode connected to a third node; a light emitting element connected between the second node and a second power supply voltage node configured to receive a second power supply voltage; a second transistor connected between a data line which is any one of the data lines and the third node, and having a gate electrode connected to a first sub-gate line which is any one of the gate lines; a first capacitor connected between the first node and the third node; a second capacitor connected between an initialization voltage node to which an initialization voltage is inputted and the third node; and a third capacitor connected between the third node and the second node.
2. The pixel of claim 1, further comprising a fourth transistor including a first electrode connected to the second node, a second electrode electrically connected to a third power line to which a voltage of an initialization power source is supplied, and a gate electrode electrically connected to a second scan line.
3. The pixel of claim 2, wherein the light emitting element is turned off when the voltage of the initialization power source is supplied to the second node.
4. The pixel of claim 2, wherein each of the first transistor to the fourth transistor is a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) including a body electrode.
5. The pixel of claim 4, wherein the voltage of the first driving power source is supplied to the body electrode of each of the first transistor to the fourth transistor.
6. The pixel of claim 2, wherein one horizontal period includes a first period, a second period, and a third period, wherein, during the first period, the second transistor, the third transistor, and the fourth transistor are set to be in a turn-on state, wherein, during the second period, the second transistor and the fourth transistor are set to be in the turn-on state, and the third transistor is set to be in a turn-off state, and wherein, during the third period, the third transistor and the fourth transistor are set to be in the turn-on state, and the second transistor is set to be in the turn-off state.
7. The pixel of claim 6, wherein a voltage of a data signal is supplied to the data line during the first period to the third period.
8. A pixel comprising: a first transistor including a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node; a second transistor connected between a data line and the third node, the second transistor including a gate electrode electrically connected to a first scan line; a third transistor connected between a first power line to which a voltage of a first driving power source is supplied and the first node, the third transistor including a gate electrode electrically connected to an emission control line; a first capacitor connected between the first node and the third node; a second capacitor connected between the second node and the third node; a third capacitor connected between the third node and the first power line; and a light emitting element connected between the second node and a second power line to which a voltage of a second driving power source is supplied.
9. The pixel of claim 8, wherein the third capacitor is supplied with the voltage of the first driving power source through the first power line.
10. The pixel of claim 8, further comprising a fourth transistor including a first electrode connected to the second node, a second electrode electrically connected to a third power line to which a voltage of an initialization power source is supplied, and a gate electrode electrically connected to a second scan line.
11. The pixel of claim 10, wherein the light emitting element is turned off when the voltage of the initialization power source is supplied to the second node.
12. The pixel of claim 10, wherein each of the first transistor to the fourth transistor is a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) including a body electrode, and the voltage of the first driving power source is supplied to the body electrode of each of the first transistor to the fourth transistor.
13. The pixel of claim 10, wherein one horizontal period includes a first period, a second period, and a third period, wherein, during the first period, the second transistor, the third transistor, and the fourth transistor are set to be in a turn-on state, wherein, during the second period, the second transistor and the fourth transistor are set to be in the turn-on state, and the third transistor is set to be in a turn-off state, wherein, during the third period, the third transistor and the fourth transistor are set to be in the turn-on state, and the second transistor is set to be in the turn-off state, and wherein a voltage of a data signal is supplied to the data line during the first period to the third period.
14. A display device comprising: pixels connected to write scan lines, initialization scan lines, data lines, and emission control lines, wherein a pixel located on an ith pixel row, where i is an integer of 0 or more, and a jth pixel column, where j is an integer of 0 or more, includes: a first transistor including a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node; a second transistor connected between a jth data line among the data lines and the third node, the second transistor being turned on when a first scan signal is supplied to a first scan line among the write scan lines; a third transistor connected between a first power line to which a voltage of a first driving power source is supplied and the first node, the third transistor being turned off when an emission control signal is supplied to a kth emission control line, where k is an integer of 0 or more; a first capacitor connected between the first node and the third node; a second capacitor connected between the second node and the third node; a third capacitor connected to the third node; and a light emitting element connected between the second node and a second power line to which a voltage of a second driving power source is supplied.
15. The display device of claim 14, wherein the third capacitor is connected between the third node and a power line.
16. The display device of claim 15, wherein the power line is the first power line or the second power line.
17. The display device of claim 14, wherein the pixel located on the ith pixel row and the jth pixel column further includes a fourth transistor including a first electrode connected to the second node and a second electrode electrically connected to a third power line to which a voltage of an initialization power source is supplied, the fourth transistor being turned on when a second scan signal is supplied to a second scan line among the initialization scan lines.
18. The display device of claim 17, wherein each of the first transistor to the fourth transistor is a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) including a body electrode, and the voltage of the first driving power source is supplied to the body electrode of each of the first transistor to the fourth transistor.
Although the claims at issue are not identical, they are not patentably distinct from each other because the scope of claim 1 of the present application overlaps and encompasses the scope of claim 1 of US Application 19/182323, and vice-versa, with the exception that claim 1 of US Application 19/182323 does not disclose the claimed aspects of:
wherein the third [node] is commonly connected to the first transistor, a first electrode of the first capacitor, a first electrode of the second capacitor, and a first electrode of the third capacitor, and wherein the initialization voltage is different from the second power supply voltage.
However, Kim does disclose that the third [node] is commonly connected to the first transistor, a first electrode of the first capacitor,… and a first electrode of the third capacitor (Yoon at Fig. 14, node N1 is commonly connected to gate of DT and capacitors C3 and C1).1
US Application 19/182323 discloses a base OLED display device upon which the claimed invention is an improvement. Yoon discloses a comparable OLED display device which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to US Application 19/182323 the teachings of Yoon for the predictable result of suppressing a flicker phenomenon (Yoon at ¶ [0014]).
The combination does not disclose that the third node is connected to a first electrode of the second capacitor, and wherein the initialization voltage is different from the second power supply voltage.
However, Luis does disclose that the third node is connected to a first electrode of the second capacitor, and wherein the initialization voltage is different from the second power supply voltage (Luis at Fig. 2B, auxiliary capacitor 240 is connected to gate of driving transistor 220 and predetermined voltage SCM which is different from VDD).
The combination of US Application 19/182323 and Yoon discloses a base OLED display device upon which the claimed invention is an improvement. Luis discloses a comparable OLED display device which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to the combination of US Application 19/182323 and Yoon the teachings of Luis for the predictable result of avoiding the problem of crosstalk (Luis at ¶ [0154]).
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12512070 in view of Yoon (US 2018/0005576 A1, Published January 4, 2018) and Luis (US 2018/0062105 A1, Published March 1, 2018).
Present Application
US Patent 12512070
1. A sub-pixel comprising:
a first transistor having a first electrode connected via a first node to a first power supply voltage node configured to receive a first power supply voltage, a second electrode connected to a second node, and a gate electrode connected to a third node;
a light emitting element connected between the second node and a second power supply voltage node configured to receive a second power supply voltage;
a second transistor connected between a data line and the third node, and having a gate electrode which is connected to a first sub-gate line;
a first capacitor connected between the first node and the third node;
a second capacitor connected between an initialization voltage node configured to receive an initialization voltage and the third node; and
a third capacitor connected between the third node and the second node.
1. An electronic device comprising:
a display device comprising:
a first transistor connected between a driving voltage line and an anode electrode of the light-emitting element;
a light-emitting element;
a second transistor connected between a data line and a gate electrode of the first transistor; a third transistor connected between a source electrode of the first transistor and the driving voltage line;
a fourth transistor connected between a drain electrode of the first transistor and an initialization voltage line;
a third capacitor connected between the gate electrode of the first transistor and the drain electrode of the first transistor,
a first capacitor connected between the gate electrode of the first transistor and a gate electrode of the fourth transistor;
a second capacitor connected between the gate electrode of the first transistor and the source electrode of the first transistor; and
wherein a capacitance of the first capacitor is greater than a capacitance of the third capacitor, and the capacitance of the third capacitor is greater than a capacitance of the second capacitor.
2. The sub-pixel of claim 1, further comprising: a third transistor connected between the first power supply voltage node and the first node, and having a gate electrode connected to an emission control line.
3. The sub-pixel of claim 2, further comprising: a fourth transistor connected between the second node and the initialization voltage node, and having a gate electrode connected to a second sub-gate line.
4. The sub-pixel of claim 3, wherein the first transistor, the second transistor and the third transistor are P-type transistors, and the fourth transistor is an N-type transistor.
5. The sub-pixel of claim 4, wherein each of the first to fourth transistors includes a body electrode, and the body electrode of each of the first to third transistors are configured to receive the first power supply voltage, and the body electrode of the fourth transistor is configured to receive the initialization voltage.
6. The sub-pixel of claim 3, wherein one horizontal period is divided into a first period, a second period, and a third period, the second transistor is turned on during the first period and the second period, the fourth transistor is turned on during the first period to the third periods, and the third transistor is turned off during the second period.
7. The sub-pixel of claim 6, wherein the data line is configured to receive a voltage of a data signal during the first period to the third period.
8. The sub-pixel of claim 6, wherein the third transistor is configured to be turned off during the first period.
9. The sub-pixel of claim 3, wherein the initialization voltage is a voltage by which the light emitting element is configured to be turned off based on the voltage being supplied to the light emitting element.
10. The sub-pixel of claim 2, further comprising: a fourth transistor connected between the second node and an auxiliary initialization voltage node configured to receive an auxiliary initialization voltage, and having a gate electrode connected to a second sub-gate line, wherein the auxiliary initialization voltage is a voltage which is different from the initialization voltage.
11. A display device comprising: sub-pixels connected to data lines, gate lines, and emission control lines; a gate driver configured to drive the gate lines and the emission control lines; and a data driver configured to drive the data lines, each of the sub-pixels comprising: a first transistor having a first electrode connected via a first node to a first power supply voltage node configured to receive a first power supply voltage, a second electrode connected to a second node, and a gate electrode connected to a third node; a light emitting element connected between the second node and a second power supply voltage node configured to receive a second power supply voltage; a second transistor connected between a data line which is any one of the data lines and the third node, and having a gate electrode connected to a first sub-gate line which is any one of the gate lines; a first capacitor connected between the first node and the third node; a second capacitor connected between an initialization voltage node to which an initialization voltage is inputted and the third node; and a third capacitor connected between the third node and the second node.
12. The display device of claim 11, wherein each of the sub-pixels further comprises a third transistor connected between the first power supply voltage node and the first node and having a gate electrode connected to an emission control line which is any one of the emission control lines.
13. The display device of claim 12, wherein each of the sub-pixels further comprises a fourth transistor connected between the second node and the initialization voltage node and having a gate electrode which is connected to a second sub-gate line which is any one of the gate lines.
14. The display device of claim 13, wherein the first transistor, the second transistor and the third transistor are P-type transistors, and the fourth transistor is an N-type transistor.
15. The display device of claim 14, wherein each of the first to fourth transistors includes a body electrode, and the body electrode of each of the first to third transistors are configured to receive the first power supply voltage, and the body electrode of the fourth transistor is configured to receive the initialization voltage.
16. The display device of claim 13, wherein one horizontal period is divided into a first period, a second period, and a third period, and the gate driver is configured to supply a first scan signal with a gate-on voltage to the first sub-gate line during the first period and the second period, to supply a second scan signal with a gate-on voltage to the second sub-gate line during the first period to the third period, and to supply an emission control signal with a gate-off voltage to the emission control line during the second period.
17. The display device of claim 16, wherein the data driver is configured to supply a voltage of a data signal to the data line during the first period to the third period.
18. The display device of claim 16, wherein the gate driver is further configured to supply the emission control signal to the emission control line during the first period.
19. The display device of claim 12, wherein each of the sub-pixels further comprises a fourth transistor connected between the second node and an auxiliary initialization voltage node to which an auxiliary initialization voltage is supplied and having a gate electrode which is connected to a second sub-gate line which is any one of the gate lines, and the auxiliary initialization voltage is a voltage which is different from the initialization voltage.
20. An electronic device, comprising a processor to provide image data; a display device to display an image based on the image data; and wherein the display device, comprising: sub-pixels connected to data lines, gate lines, and emission control lines; a gate driver configured to drive the gate lines and the emission control lines; and a data driver configured to drive the data lines, each of the sub-pixels comprising: a first transistor having a first electrode connected via a first node to a first power supply voltage node configured to receive a first power supply voltage, a second electrode connected to a second node, and a gate electrode connected to a third node; a light emitting element connected between the second node and a second power supply voltage node configured to receive a second power supply voltage; a second transistor connected between a data line which is any one of the data lines and the third node, and having a gate electrode connected to a first sub-gate line which is any one of the gate lines; a first capacitor connected between the first node and the third node; a second capacitor connected between an initialization voltage node to which an initialization voltage is inputted and the third node; and a third capacitor connected between the third node and the second node.
2. The electronic device of claim 1, wherein the capacitance of the third capacitor is 31.3% of the capacitance of the second capacitor, and the capacitance of the first capacitor is 18.8% of the capacitance of the second capacitor.
3. The electronic device of claim 1, further comprising: a first scan line connected to a gate electrode of the second transistor; an emission control line connected to a gate electrode of the third transistor; and a second scan line connected to the gate electrode of the fourth transistor.
4. The electronic device of claim 3, wherein in an initialization/write period, an emission control signal of the emission control line, a first scan signal of the first scan line, and a second scan signal of the second scan line each have an active level, in a compensation period, the first scan signal and the second scan signal each have an active level, in a bypass period, the emission control signal and the second scan signal each have an active level, and the first scan signal has a non-active level, and in an emission period, the emission control signal has an active level, and the first scan signal and the second scan signal each have a non-active level.
5. The electronic device of claim 4, wherein in the initialization/write period and the compensation period, a previous data voltage is applied to the data line, in the emission period, a current data voltage is applied to the data line, and in the bypass period, a transient data voltage which transitions from the previous data voltage to the current data voltage is applied to the data line.
6. The electronic device of claim 1, wherein at least one of the first transistor, the second transistor, the third transistor, and the fourth transistor includes a body electrode connected to the driving voltage line.
7. The electronic device of claim 1, wherein an initialization voltage of the initialization voltage line is lower than a driving voltage of the driving voltage line.
8. The electronic device of claim 1, further comprising a common voltage line connected to a cathode electrode of the light-emitting element.
9. The electronic device of claim 8, wherein an initialization voltage of the initialization voltage line is higher than a common voltage of the common voltage line.
10. A display device comprising: a light-emitting element; a first transistor connected between a driving voltage line and an anode electrode of the light-emitting element; a second transistor connected between a data line and the gate electrode of the first transistor; a third transistor connected between a source electrode of the first transistor and the driving voltage line; a fourth transistor connected between a drain electrode of the first transistor and an initialization voltage line; a first capacitor connected between a gate electrode of the first transistor and a gate electrode of the fourth transistor; a second capacitor connected between the gate electrode of the first transistor and the source electrode of the first transistor; a third capacitor connected between the gate electrode of the first transistor and the drain electrode of the first transistor, wherein a capacitance of the first capacitor is greater than a capacitance of the third capacitor, and the capacitance of the third capacitor is greater than a capacitance of the second capacitor.
11. The display device of claim 10, wherein the capacitance of the third capacitor is 31.3% of the capacitance of the second capacitor, and the capacitance of the first capacitor is 18.8% of the capacitance of the second capacitor.
12. The display device of claim 10, further comprising: a first scan line connected to a gate electrode of the second transistor; an emission control line connected to a gate electrode of the third transistor; and a second scan line connected to the gate electrode of the fourth transistor.
13. The display device of claim 12, wherein in an initialization/write period, an emission control signal of the emission control line, a first scan signal of the first scan line, and a second scan signal of the second scan line each have an active level, in a compensation period, the first scan signal and the second scan signal each have an active level, in a bypass period, the emission control signal and the second scan signal each have an active level, and the first scan signal has a non-active level, and in an emission period, the emission control signal has an active level, and the first scan signal and the second scan signal each have a non-active level.
14. The display device of claim 13, wherein in the initialization/write period and the compensation period, a previous data voltage is applied to the data line, in the emission period, a current data voltage is applied to the data line, and in the bypass period, a transient data voltage which transitions from the previous data voltage to the current data voltage is applied to the data line.
15. The display device of claim 10, wherein at least one of the first transistor, the second transistor, the third transistor, and the fourth transistor includes a body electrode connected to the driving voltage line.
Although the claims at issue are not identical, they are not patentably distinct from each other because the scope of claim 1 of the present application overlaps and encompasses the scope of claim 1 of US Patent 12512070, and vice-versa, with the exception that claims 1 of US Patent 12512070 does not disclose the claimed aspects of:
wherein the third [node] is commonly connected to the first transistor, a first electrode of the first capacitor, a first electrode of the second capacitor, and a first electrode of the third capacitor, and wherein the initialization voltage is different from the second power supply voltage.
However, Yoon does disclose that the third [node] is commonly connected to the first transistor, a first electrode of the first capacitor,… and a first electrode of the third capacitor (Yoon at Fig. 14, node N1 is commonly connected to gate of DT and capacitors C3 and C1).2
US Patent 12512070 discloses a base OLED display device upon which the claimed invention is an improvement. Yoon discloses a comparable OLED display device which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to US Patent 12512070 the teachings of Yoon for the predictable result of suppressing a flicker phenomenon (Yoon at ¶ [0014]).
The combination does not disclose that the third node is connected to a first electrode of the second capacitor, and wherein the initialization voltage is different from the second power supply voltage.
However, Luis does disclose that the third node is connected to a first electrode of the second capacitor, and wherein the initialization voltage is different from the second power supply voltage (Luis at Fig. 2B, auxiliary capacitor 240 is connected to gate of driving transistor 220 and predetermined voltage SCM which is different from VDD).
The combination of US Patent 12512070 and Yoon discloses a base OLED display device upon which the claimed invention is an improvement. Luis discloses a comparable OLED display device which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to the combination of US Patent 12512070 and Yoon the teachings of Luis for the predictable result of avoiding the problem of crosstalk (Luis at ¶ [0154]).
Claims 1-2 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12437705 in view of Yoon (US 2018/0005576 A1, Published January 4, 2018) and Luis (US 2018/0062105 A1, Published March 1, 2018).
Present Application
US Patent 12437705
1. A sub-pixel comprising:
a first transistor having a first electrode connected via a first node to a first power supply voltage node configured to receive a first power supply voltage, a second electrode connected to a second node, and a gate electrode connected to a third node;
a light emitting element connected between the second node and a second power supply voltage node configured to receive a second power supply voltage;
a second transistor connected between a data line and the third node, and having a gate electrode which is connected to a first sub-gate line;
[Claim 2] 2. The sub-pixel of claim 1, further comprising: a third transistor connected between the first power supply voltage node and the first node, and having a gate electrode connected to an emission control line
a first capacitor connected between the first node and the third node;
a second capacitor connected between an initialization voltage node configured to receive an initialization voltage and the third node; and
a third capacitor connected between the third node and the second node.
1. A pixel comprising:
a first transistor including a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node;
a light emitting element connected between the second node and the second power line.
a second transistor connected between a data line and the third node, the second transistor including a gate electrode electrically connected to a first scan line;
a third transistor connected between a first power line to which a voltage of a first driving power source is supplied and the first node, the third transistor including a gate electrode electrically connected to an emission control line;
a first capacitor connected between the first node and the third node;
a third capacitor connected between the third node and a second power line to which a voltage of a second driving power source is supplied; and
a second capacitor connected between the second node and the third node;
.3. The sub-pixel of claim 2, further comprising: a fourth transistor connected between the second node and the initialization voltage node, and having a gate electrode connected to a second sub-gate line.
4. The sub-pixel of claim 3, wherein the first transistor, the second transistor and the third transistor are P-type transistors, and the fourth transistor is an N-type transistor.
5. The sub-pixel of claim 4, wherein each of the first to fourth transistors includes a body electrode, and the body electrode of each of the first to third transistors are configured to receive the first power supply voltage, and the body electrode of the fourth transistor is configured to receive the initialization voltage.
6. The sub-pixel of claim 3, wherein one horizontal period is divided into a first period, a second period, and a third period, the second transistor is turned on during the first period and the second period, the fourth transistor is turned on during the first period to the third periods, and the third transistor is turned off during the second period.
7. The sub-pixel of claim 6, wherein the data line is configured to receive a voltage of a data signal during the first period to the third period.
8. The sub-pixel of claim 6, wherein the third transistor is configured to be turned off during the first period.
9. The sub-pixel of claim 3, wherein the initialization voltage is a voltage by which the light emitting element is configured to be turned off based on the voltage being supplied to the light emitting element.
10. The sub-pixel of claim 2, further comprising: a fourth transistor connected between the second node and an auxiliary initialization voltage node configured to receive an auxiliary initialization voltage, and having a gate electrode connected to a second sub-gate line, wherein the auxiliary initialization voltage is a voltage which is different from the initialization voltage.
11. A display device comprising: sub-pixels connected to data lines, gate lines, and emission control lines; a gate driver configured to drive the gate lines and the emission control lines; and a data driver configured to drive the data lines, each of the sub-pixels comprising: a first transistor having a first electrode connected via a first node to a first power supply voltage node configured to receive a first power supply voltage, a second electrode connected to a second node, and a gate electrode connected to a third node; a light emitting element connected between the second node and a second power supply voltage node configured to receive a second power supply voltage; a second transistor connected between a data line which is any one of the data lines and the third node, and having a gate electrode connected to a first sub-gate line which is any one of the gate lines; a first capacitor connected between the first node and the third node; a second capacitor connected between an initialization voltage node to which an initialization voltage is inputted and the third node; and a third capacitor connected between the third node and the second node.
12. The display device of claim 11, wherein each of the sub-pixels further comprises a third transistor connected between the first power supply voltage node and the first node and having a gate electrode connected to an emission control line which is any one of the emission control lines.
13. The display device of claim 12, wherein each of the sub-pixels further comprises a fourth transistor connected between the second node and the initialization voltage node and having a gate electrode which is connected to a second sub-gate line which is any one of the gate lines.
14. The display device of claim 13, wherein the first transistor, the second transistor and the third transistor are P-type transistors, and the fourth transistor is an N-type transistor.
15. The display device of claim 14, wherein each of the first to fourth transistors includes a body electrode, and the body electrode of each of the first to third transistors are configured to receive the first power supply voltage, and the body electrode of the fourth transistor is configured to receive the initialization voltage.
16. The display device of claim 13, wherein one horizontal period is divided into a first period, a second period, and a third period, and the gate driver is configured to supply a first scan signal with a gate-on voltage to the first sub-gate line during the first period and the second period, to supply a second scan signal with a gate-on voltage to the second sub-gate line during the first period to the third period, and to supply an emission control signal with a gate-off voltage to the emission control line during the second period.
17. The display device of claim 16, wherein the data driver is configured to supply a voltage of a data signal to the data line during the first period to the third period.
18. The display device of claim 16, wherein the gate driver is further configured to supply the emission control signal to the emission control line during the first period.
19. The display device of claim 12, wherein each of the sub-pixels further comprises a fourth transistor connected between the second node and an auxiliary initialization voltage node to which an auxiliary initialization voltage is supplied and having a gate electrode which is connected to a second sub-gate line which is any one of the gate lines, and the auxiliary initialization voltage is a voltage which is different from the initialization voltage.
20. An electronic device, comprising a processor to provide image data; a display device to display an image based on the image data; and wherein the display device, comprising: sub-pixels connected to data lines, gate lines, and emission control lines; a gate driver configured to drive the gate lines and the emission control lines; and a data driver configured to drive the data lines, each of the sub-pixels comprising: a first transistor having a first electrode connected via a first node to a first power supply voltage node configured to receive a first power supply voltage, a second electrode connected to a second node, and a gate electrode connected to a third node; a light emitting element connected between the second node and a second power supply voltage node configured to receive a second power supply voltage; a second transistor connected between a data line which is any one of the data lines and the third node, and having a gate electrode connected to a first sub-gate line which is any one of the gate lines; a first capacitor connected between the first node and the third node; a second capacitor connected between an initialization voltage node to which an initialization voltage is inputted and the third node; and a third capacitor connected between the third node and the second node.
2. The pixel of claim 1, further comprising a fourth transistor including a first electrode connected to the second node, a second electrode electrically connected to a third power line to which a voltage of an initialization power source is supplied, and a gate electrode electrically connected to a second scan line.
3. The pixel of claim 2, wherein the light emitting element is turned off when the voltage of the initialization power source is supplied to the second node.
4. The pixel of claim 2, wherein each of the first transistor to the fourth transistor is a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) including a body electrode.
5. The pixel of claim 4, wherein the voltage of the first driving power source is supplied to the body electrode of each of the first transistor to the fourth transistor.
6. The pixel of claim 2, wherein one horizontal period includes a first period, a second period, and a third period, wherein, during the first period, the second transistor, the third transistor, and the fourth transistor are set to be in a turn-on state, wherein, during the second period, the second transistor and the fourth transistor are set to be in the turn-on state, and the third transistor is set to be in a turn-off state, and wherein, during the third period, the third transistor and the fourth transistor are set to be in the turn-on state, and the second transistor is set to be in the turn-off state.
7. The pixel of claim 6, wherein a voltage of a data signal is supplied to the data line during the first period to the third period.
8. A pixel comprising: a first transistor including a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node; a second transistor connected between a data line and the third node, the second transistor including a gate electrode electrically connected to a first scan line; a third transistor connected between a first power line to which a voltage of a first driving power source is supplied and the first node, the third transistor including a gate electrode electrically connected to an emission control line; a first capacitor connected between the first node and the third node; a second capacitor connected between the second node and the third node; a third capacitor connected between the third node and the first power line; and a light emitting element connected between the second node and a second power line to which a voltage of a second driving power source is supplied.
9. The pixel of claim 8, wherein the third capacitor is supplied with the voltage of the first driving power source through the first power line.
10. The pixel of claim 8, further comprising a fourth transistor including a first electrode connected to the second node, a second electrode electrically connected to a third power line to which a voltage of an initialization power source is supplied, and a gate electrode electrically connected to a second scan line.
11. The pixel of claim 10, wherein the light emitting element is turned off when the voltage of the initialization power source is supplied to the second node.
12. The pixel of claim 10, wherein each of the first transistor to the fourth transistor is a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) including a body electrode, and the voltage of the first driving power source is supplied to the body electrode of each of the first transistor to the fourth transistor.
13. The pixel of claim 10, wherein one horizontal period includes a first period, a second period, and a third period, wherein, during the first period, the second transistor, the third transistor, and the fourth transistor are set to be in a turn-on state, wherein, during the second period, the second transistor and the fourth transistor are set to be in the turn-on state, and the third transistor is set to be in a turn-off state, wherein, during the third period, the third transistor and the fourth transistor are set to be in the turn-on state, and the second transistor is set to be in the turn-off state, and wherein a voltage of a data signal is supplied to the data line during the first period to the third period.
14. A display device comprising: pixels connected to write scan lines, initialization scan lines, data lines, and emission control lines, wherein a pixel located on an ith pixel row, where i is an integer of 0 or more, and a jth pixel column, where j is an integer of 0 or more, includes: a first transistor including a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node; a second transistor connected between a jth data line among the data lines and the third node, the second transistor being turned on when a first scan signal is supplied to a first scan line among the write scan lines; a third transistor connected between a first power line to which a voltage of a first driving power source is supplied and the first node, the third transistor being turned off when an emission control signal is supplied to a kth emission control line, where k is an integer of 0 or more; a first capacitor connected between the first node and the third node; a second capacitor connected between the second node and the third node; a third capacitor connected to the third node; and a light emitting element connected between the second node and a second power line to which a voltage of a second driving power source is supplied.
15. The display device of claim 14, wherein the third capacitor is connected between the third node and a power line.
16. The display device of claim 15, wherein the power line is the first power line or the second power line.
17. The display device of claim 14, wherein the pixel located on the ith pixel row and the jth pixel column further includes a fourth transistor including a first electrode connected to the second node and a second electrode electrically connected to a third power line to which a voltage of an initialization power source is supplied, the fourth transistor being turned on when a second scan signal is supplied to a second scan line among the initialization scan lines.
18. The display device of claim 17, wherein each of the first transistor to the fourth transistor is a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) including a body electrode, and the voltage of the first driving power source is supplied to the body electrode of each of the first transistor to the fourth transistor.
Although the claims at issue are not identical, they are not patentably distinct from each other because the scope of claims 1-2 of the present application overlaps and encompasses the scope of claim 1 of US Patent 12437705, and vice-versa, with the exception that claims 1 of US Patent 12437705 does not disclose the claimed aspects of:
wherein the third [node] is commonly connected to the first transistor, a first electrode of the first capacitor, a first electrode of the second capacitor, and a first electrode of the third capacitor, and wherein the initialization voltage is different from the second power supply voltage.
However, Yoon does disclose that the third [node] is commonly connected to the first transistor, a first electrode of the first capacitor,… and a first electrode of the third capacitor (Yoon at Fig. 14, node N1 is commonly connected to gate of DT and capacitors C3 and C1). 3
US Patent 12437705 discloses a base OLED display device upon which the claimed invention is an improvement. Yoon discloses a comparable OLED display device which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to US Patent 12437705 the teachings of Yoon for the predictable result of suppressing a flicker phenomenon (Yoon at ¶ [0014]).
The combination does not disclose that the third node is connected to a first electrode of the second capacitor, and wherein the initialization voltage is different from the second power supply voltage.
However, Luis does disclose that the third node is connected to a first electrode of the second capacitor, and wherein the initialization voltage is different from the second power supply voltage (Luis at Fig. 2B, auxiliary capacitor 240 is connected to gate of driving transistor 220 and predetermined voltage SCM which is different from VDD).
The combination of US Patent 12437705 and Yoon discloses a base OLED display device upon which the claimed invention is an improvement. Luis discloses a comparable OLED display device which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to the combination of US Patent 12437705 and Yoon the teachings of Luis for the predictable result of avoiding the problem of crosstalk (Luis at ¶ [0154]).
Claims 1-2 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of copending Application No. 19/09679 (reference application) in view of Yoon (US 2018/0005576 A1, Published January 4, 2018) and Luis (US 2018/0062105 A1, Published March 1, 2018).
Present Application
US Application 19/09679
1. A sub-pixel comprising:
a first transistor having a first electrode connected via a first node to a first power supply voltage node configured to receive a first power supply voltage, a second electrode connected to a second node, and a gate electrode connected to a third node;
a light emitting element connected between the second node and a second power supply voltage node configured to receive a second power supply voltage;
a second transistor connected between a data line and the third node, and having a gate electrode which is connected to a first sub-gate line;
[Claim 2] 2. The sub-pixel of claim 1, further comprising: a third transistor connected between the first power supply voltage node and the first node, and having a gate electrode connected to an emission control line
a first capacitor connected between the first node and the third node;
a second capacitor connected between an initialization voltage node configured to receive an initialization voltage and the third node; and
a third capacitor connected between the third node and the second node.
1. A pixel comprising:
a first transistor including: a first electrode connected to a first node; a second electrode connected to a second node; and a gate electrode connected to a third node;
a light-emitting element connected between the second node and a second power line to which second driving power is supplied.
a second transistor connected between a data line and the third node, the second transistor including: a gate electrode electrically connected to a first scan line;
a third transistor connected between a first power line to which first driving power is supplied, and the first node, the third transistor including: a gate electrode electrically connected to an emission control line;
a first capacitor connected between the first node and the third node;
a second capacitor connected between the third node and a reference power line to which reference power is supplied;
a third capacitor connected between the second node and the third node; and
2. The pixel according to claim 1, further comprising a fourth transistor including a first electrode connected to the second node, a second electrode electrically connected to a third power line to which initialization power is supplied, and a gate electrode electrically connected to a second scan line.
3. The pixel according to claim 2, wherein a voltage level of the reference power is lower than a voltage level of the first driving power, and is higher than a voltage level of the initialization power.
4. The pixel according to claim 2, wherein a voltage level of the reference power is equal to a voltage level of the first driving power, and wherein the reference power line is the first power line.
5. The pixel according to claim 2, wherein, when a voltage of the initialization power is supplied to the second node, the light-emitting element is turned off.
6. The pixel according to claim 2, wherein each of the first transistor to the fourth transistor comprises a metal-oxide-semiconductor field-effect transistor including a body electrode.
7. The pixel according to claim 6, wherein a voltage of the first driving power is supplied to the body electrode of each of the first transistor to the fourth transistor.
8. The pixel according to claim 2, wherein a horizontal period includes a first period, a second period, and a third period, wherein, during the first period, the second transistor, the third transistor, and the fourth transistor are set to a turn-on state, wherein, during the second period, the second transistor and the fourth transistor are set to the turn-on state, and the third transistor is set to a turn-off state, and wherein, during the third period, the third transistor and the fourth transistor are set to the turn-on state, and the second transistor is set to the turn-off state.
9. The pixel according to claim 8, wherein, during the first period to the third period, a voltage of a data signal is supplied to the data line.
10. The pixel according to claim 1, wherein each of the first capacitor to the third capacitor includes a metal-oxide-metal capacitor or a metal-insulator-metal capacitor.
11. The pixel according to claim 1, wherein each of the first capacitor and the second capacitor includes a metal-oxide-metal capacitor or a metal-insulator-metal capacitor, and wherein the third capacitor includes a parasitic capacitor.
12. A display device comprising: pixels connected to write scan lines, initialization scan lines, data lines, and emission control lines, the pixels including: a pixel disposed on an i-th pixel row and a j-th pixel column, i and j respectively being natural numbers greater than zero, the pixel comprising: a first transistor including a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node; a second transistor connected between a j-th data line among the data lines and the third node, and configured to be turned on when a first scan signal is supplied to a first scan line among the write scan lines; a third transistor connected between a first power line to which a voltage of first driving power is supplied and the first node, and configured to be turned off when an emission control signal is supplied to a k-th emission control line, k being a natural number greater than zero; a first capacitor connected between the first node and the third node; a second capacitor connected between the third node and a reference power line to which reference power is supplied; a third capacitor connected between the second node and the third node; and a light-emitting element connected between the second node and a second power line to which second driving power is supplied.
13. The display device according to claim 12, wherein the pixel disposed on the i-th pixel row and the j-th pixel column further comprises a fourth transistor including a first electrode connected to the second node, and a second electrode electrically connected to a third power line to which initialization power is supplied, the fourth transistor being configured to be turned on when a second scan signal is supplied to a second scan line.
14. The display device according to claim 13, wherein a voltage level of the reference power is lower than a voltage level of the first driving power, and is higher than a voltage level of the initialization power.
15. The display device according to claim 13, wherein a voltage level of the reference power is equal to a voltage level of the first driving power, and wherein the reference power line is the first power line.
16. The display device according to claim 15, wherein each of the first transistor to the fourth transistor includes a metal-oxide-semiconductor field-effect transistor including a body electrode, and the voltage of the first driving power is supplied to the body electrode.
17. An electronic device comprising: a processor to provide input image data; and a display device to display an image based on the input image data, the display device comprising: pixels connected to write scan lines, initialization scan lines, data lines, and emission control lines, the pixels including: a pixel disposed on an i-th pixel row and a j-th pixel column, i and j respectively being natural numbers greater than zero, the pixel comprising: a first transistor including a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node; a second transistor connected between a j-th data line among the data lines and the third node, and configured to be turned on when a first scan signal is supplied to a first scan line among the write scan lines; a third transistor connected between a first power line to which a voltage of first driving power is supplied and the first node, and configured to be turned off when an emission control signal is supplied to a k-th emission control line, k being a natural number greater than zero; a first capacitor connected between the first node and the third node; a second capacitor connected between the third node and a reference power line to which reference power is supplied; a third capacitor connected between the second node and the third node; and a light-emitting element connected between the second node and a second power line to which second driving power is supplied.
.3. The sub-pixel of claim 2, further comprising: a fourth transistor connected between the second node and the initialization voltage node, and having a gate electrode connected to a second sub-gate line.
4. The sub-pixel of claim 3, wherein the first transistor, the second transistor and the third transistor are P-type transistors, and the fourth transistor is an N-type transistor.
5. The sub-pixel of claim 4, wherein each of the first to fourth transistors includes a body electrode, and the body electrode of each of the first to third transistors are configured to receive the first power supply voltage, and the body electrode of the fourth transistor is configured to receive the initialization voltage.
6. The sub-pixel of claim 3, wherein one horizontal period is divided into a first period, a second period, and a third period, the second transistor is turned on during the first period and the second period, the fourth transistor is turned on during the first period to the third periods, and the third transistor is turned off during the second period.
7. The sub-pixel of claim 6, wherein the data line is configured to receive a voltage of a data signal during the first period to the third period.
8. The sub-pixel of claim 6, wherein the third transistor is configured to be turned off during the first period.
9. The sub-pixel of claim 3, wherein the initialization voltage is a voltage by which the light emitting element is configured to be turned off based on the voltage being supplied to the light emitting element.
10. The sub-pixel of claim 2, further comprising: a fourth transistor connected between the second node and an auxiliary initialization voltage node configured to receive an auxiliary initialization voltage, and having a gate electrode connected to a second sub-gate line, wherein the auxiliary initialization voltage is a voltage which is different from the initialization voltage.
11. A display device comprising: sub-pixels connected to data lines, gate lines, and emission control lines; a gate driver configured to drive the gate lines and the emission control lines; and a data driver configured to drive the data lines, each of the sub-pixels comprising: a first transistor having a first electrode connected via a first node to a first power supply voltage node configured to receive a first power supply voltage, a second electrode connected to a second node, and a gate electrode connected to a third node; a light emitting element connected between the second node and a second power supply voltage node configured to receive a second power supply voltage; a second transistor connected between a data line which is any one of the data lines and the third node, and having a gate electrode connected to a first sub-gate line which is any one of the gate lines; a first capacitor connected between the first node and the third node; a second capacitor connected between an initialization voltage node to which an initialization voltage is inputted and the third node; and a third capacitor connected between the third node and the second node.
12. The display device of claim 11, wherein each of the sub-pixels further comprises a third transistor connected between the first power supply voltage node and the first node and having a gate electrode connected to an emission control line which is any one of the emission control lines.
13. The display device of claim 12, wherein each of the sub-pixels further comprises a fourth transistor connected between the second node and the initialization voltage node and having a gate electrode which is connected to a second sub-gate line which is any one of the gate lines.
14. The display device of claim 13, wherein the first transistor, the second transistor and the third transistor are P-type transistors, and the fourth transistor is an N-type transistor.
15. The display device of claim 14, wherein each of the first to fourth transistors includes a body electrode, and the body electrode of each of the first to third transistors are configured to receive the first power supply voltage, and the body electrode of the fourth transistor is configured to receive the initialization voltage.
16. The display device of claim 13, wherein one horizontal period is divided into a first period, a second period, and a third period, and the gate driver is configured to supply a first scan signal with a gate-on voltage to the first sub-gate line during the first period and the second period, to supply a second scan signal with a gate-on voltage to the second sub-gate line during the first period to the third period, and to supply an emission control signal with a gate-off voltage to the emission control line during the second period.
17. The display device of claim 16, wherein the data driver is configured to supply a voltage of a data signal to the data line during the first period to the third period.
18. The display device of claim 16, wherein the gate driver is further configured to supply the emission control signal to the emission control line during the first period.
19. The display device of claim 12, wherein each of the sub-pixels further comprises a fourth transistor connected between the second node and an auxiliary initialization voltage node to which an auxiliary initialization voltage is supplied and having a gate electrode which is connected to a second sub-gate line which is any one of the gate lines, and the auxiliary initialization voltage is a voltage which is different from the initialization voltage.
20. An electronic device, comprising a processor to provide image data; a display device to display an image based on the image data; and wherein the display device, comprising: sub-pixels connected to data lines, gate lines, and emission control lines; a gate driver configured to drive the gate lines and the emission control lines; and a data driver configured to drive the data lines, each of the sub-pixels comprising: a first transistor having a first electrode connected via a first node to a first power supply voltage node configured to receive a first power supply voltage, a second electrode connected to a second node, and a gate electrode connected to a third node; a light emitting element connected between the second node and a second power supply voltage node configured to receive a second power supply voltage; a second transistor connected between a data line which is any one of the data lines and the third node, and having a gate electrode connected to a first sub-gate line which is any one of the gate lines; a first capacitor connected between the first node and the third node; a second capacitor connected between an initialization voltage node to which an initialization voltage is inputted and the third node; and a third capacitor connected between the third node and the second node.
2. The pixel of claim 1, further comprising a fourth transistor including a first electrode connected to the second node, a second electrode electrically connected to a third power line to which a voltage of an initialization power source is supplied, and a gate electrode electrically connected to a second scan line.
3. The pixel of claim 2, wherein the light emitting element is turned off when the voltage of the initialization power source is supplied to the second node.
4. The pixel of claim 2, wherein each of the first transistor to the fourth transistor is a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) including a body electrode.
5. The pixel of claim 4, wherein the voltage of the first driving power source is supplied to the body electrode of each of the first transistor to the fourth transistor.
6. The pixel of claim 2, wherein one horizontal period includes a first period, a second period, and a third period, wherein, during the first period, the second transistor, the third transistor, and the fourth transistor are set to be in a turn-on state, wherein, during the second period, the second transistor and the fourth transistor are set to be in the turn-on state, and the third transistor is set to be in a turn-off state, and wherein, during the third period, the third transistor and the fourth transistor are set to be in the turn-on state, and the second transistor is set to be in the turn-off state.
7. The pixel of claim 6, wherein a voltage of a data signal is supplied to the data line during the first period to the third period.
8. A pixel comprising: a first transistor including a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node; a second transistor connected between a data line and the third node, the second transistor including a gate electrode electrically connected to a first scan line; a third transistor connected between a first power line to which a voltage of a first driving power source is supplied and the first node, the third transistor including a gate electrode electrically connected to an emission control line; a first capacitor connected between the first node and the third node; a second capacitor connected between the second node and the third node; a third capacitor connected between the third node and the first power line; and a light emitting element connected between the second node and a second power line to which a voltage of a second driving power source is supplied.
9. The pixel of claim 8, wherein the third capacitor is supplied with the voltage of the first driving power source through the first power line.
10. The pixel of claim 8, further comprising a fourth transistor including a first electrode connected to the second node, a second electrode electrically connected to a third power line to which a voltage of an initialization power source is supplied, and a gate electrode electrically connected to a second scan line.
11. The pixel of claim 10, wherein the light emitting element is turned off when the voltage of the initialization power source is supplied to the second node.
12. The pixel of claim 10, wherein each of the first transistor to the fourth transistor is a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) including a body electrode, and the voltage of the first driving power source is supplied to the body electrode of each of the first transistor to the fourth transistor.
13. The pixel of claim 10, wherein one horizontal period includes a first period, a second period, and a third period, wherein, during the first period, the second transistor, the third transistor, and the fourth transistor are set to be in a turn-on state, wherein, during the second period, the second transistor and the fourth transistor are set to be in the turn-on state, and the third transistor is set to be in a turn-off state, wherein, during the third period, the third transistor and the fourth transistor are set to be in the turn-on state, and the second transistor is set to be in the turn-off state, and wherein a voltage of a data signal is supplied to the data line during the first period to the third period.
14. A display device comprising: pixels connected to write scan lines, initialization scan lines, data lines, and emission control lines, wherein a pixel located on an ith pixel row, where i is an integer of 0 or more, and a jth pixel column, where j is an integer of 0 or more, includes: a first transistor including a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node; a second transistor connected between a jth data line among the data lines and the third node, the second transistor being turned on when a first scan signal is supplied to a first scan line among the write scan lines; a third transistor connected between a first power line to which a voltage of a first driving power source is supplied and the first node, the third transistor being turned off when an emission control signal is supplied to a kth emission control line, where k is an integer of 0 or more; a first capacitor connected between the first node and the third node; a second capacitor connected between the second node and the third node; a third capacitor connected to the third node; and a light emitting element connected between the second node and a second power line to which a voltage of a second driving power source is supplied.
15. The display device of claim 14, wherein the third capacitor is connected between the third node and a power line.
16. The display device of claim 15, wherein the power line is the first power line or the second power line.
17. The display device of claim 14, wherein the pixel located on the ith pixel row and the jth pixel column further includes a fourth transistor including a first electrode connected to the second node and a second electrode electrically connected to a third power line to which a voltage of an initialization power source is supplied, the fourth transistor being turned on when a second scan signal is supplied to a second scan line among the initialization scan lines.
18. The display device of claim 17, wherein each of the first transistor to the fourth transistor is a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) including a body electrode, and the voltage of the first driving power source is supplied to the body electrode of each of the first transistor to the fourth transistor.
Although the claims at issue are not identical, they are not patentably distinct from each other because the scope of claims 1-2 of the present application overlaps and encompasses the scope of claim 1 of US Application 19/09679, and vice-versa, with the exception that claim 1 of US Application 19/09679 does not disclose the claimed aspects of:
wherein the third [node] is commonly connected to the first transistor, a first electrode of the first capacitor, a first electrode of the second capacitor, and a first electrode of the third capacitor, and wherein the initialization voltage is different from the second power supply voltage.
However, Yoon does disclose that the third [node] is commonly connected to the first transistor, a first electrode of the first capacitor,… and a first electrode of the third capacitor (Yoon at Fig. 14, node N1 is commonly connected to gate of DT and capacitors C3 and C1). 4
US Application 19/09679 discloses a base OLED display device upon which the claimed invention is an improvement. Yoon discloses a comparable OLED display device which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to US Application 19/09679 the teachings of Yoon for the predictable result of suppressing a flicker phenomenon (Yoon at ¶ [0014]).
The combination does not disclose that the third node is connected to a first electrode of the second capacitor, and wherein the initialization voltage is different from the second power supply voltage.
However, Luis does disclose that the third node is connected to a first electrode of the second capacitor, and wherein the initialization voltage is different from the second power supply voltage (Luis at Fig. 2B, auxiliary capacitor 240 is connected to gate of driving transistor 220 and predetermined voltage SCM which is different from VDD).
The combination of US Application 19/09679 and Yoon discloses a base OLED display device upon which the claimed invention is an improvement. Luis discloses a comparable OLED display device which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to the combination of US Application 19/09679 and Yoon the teachings of Luis for the predictable result of avoiding the problem of crosstalk (Luis at ¶ [0154]).
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention..
As to claim 1, in the amended claim language “wherein the third is commonly connected to the first transistor, the second transistor, a first electrode of the first capacitor, a first electrode of the second capacitor, and a first electrode of the third capacitor….” There is lack of antecedent basis for “the third.” Examiner will assume the claim recites “the third node.” Also, the “a” should be replaced with “the” for each recitation of “first electrode” in the amended claim language.
In addition, regarding claims 1, 14 and 20, Examiner will regard the claim language “a second capacitor including a first electrode and a second electrode, wherein the first electrode is connected to the third node and the second node is connected to the first node” and “a second capacitor… the second node is connected to an initialization voltage line” as reciting “electrode” not “node” as written.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 11-13, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2009/0309516 A1, Published December 17, 2009) in view of Luis (US 2018/0062105 A1, Published March 1, 2018).
As to claim 1, Kim discloses a sub-pixel comprising:
a first transistor having a first electrode connected via a first node to a first power supply voltage node configured to receive a first power supply voltage, a second electrode connected to a second node, and a gate electrode connected to a third node (Kim at Fig. 4, transistor M2);
a light emitting element connected between the second node and a second power supply voltage node configured to receive a second power supply voltage (Kim at 4, OLED);
a second transistor connected between a data line and the third node, and having a gate electrode which is connected to a first sub-gate line (Kim at Fig. 4, transistor M1);
a first capacitor including a first electrode and a second electrode, wherein the first electrode is connected to the third node and the second node [electrode] is connected to the first node (Kim at Fig. 4, capacitor C1)…
a third capacitor including a first electrode and a second electrode, wherein the first electrode is connected to the third node (Kim at Fig. 4, capacitor C3).
Kim does not disclose that the second electrode of the third capacitor is connected to the second node.
Kim does not disclose a second capacitor including a first electrode and a second electrode, wherein the first electrode is connected to the third node and the second node [electrode] is connected to an initialization voltage node configured to receive an initialization voltage; and wherein the initialization voltage is different from the second power supply voltage.
However, Luis does disclose that the second electrode of the third capacitor is connected to the second node (Luis at Fig. 2B, capacitor Cst is connected to the source of transistor 220)
Luis also discloses a second capacitor including a first electrode and a second electrode, wherein the first electrode is connected to the third node and the second node [electrode] is connected to an initialization voltage node configured to receive an initialization voltage (Luis at Fig. 2B, capacitor 250 is connected between gate of transistor 220 and predetermined voltage SCM); and
wherein the initialization voltage is different from the second power supply voltage (Luis at ¶ [0050] discloses “In one embodiment, the absolute value of the level of the predetermined voltage S.sub.CM is greater than 0.”).
Kim discloses a base OLED display device upon which the claimed invention is an improvement. Luis discloses a comparable OLED display device which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to Kim the teachings of Luis for the predictable result of avoiding the problem of crosstalk (Luis at ¶ [0154]).
The combination of Kim and Luis results in wherein the third is commonly connected to the first transistor, the second transistor, a [the] first electrode of the first capacitor, a [the] first electrode of the second capacitor, and a [the] first electrode of the third capacitor (Kim at Fig. 4; Luis at Fig. 2B).
Kim discloses a base OLED display device upon which the claimed invention is an improvement. Luis discloses a comparable OLED display device which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to Kim the teachings of Luis for the predictable result of avoiding the problem of crosstalk (Luis at ¶ [0154]).
As to claim 2, the combination of Kim and Luis discloses the sub-pixel of claim 1, further comprising: a third transistor connected between the first power supply voltage node and the first node, and having a gate electrode connected to an emission control line (Kim at Fig. 4, transistor M3).
As to claim 3, the combination of Kim and Luis discloses the sub-pixel of claim 2, further comprising: a fourth transistor connected between the second node and the initialization voltage node, and having a gate electrode connected to a second sub-gate line (Luis at Fig. 2B, transistor 230).5
As to claim 11, Kim discloses a display device comprising: sub-pixels connected to data lines, gate lines, and emission control lines; a gate driver configured to drive the gate lines and the emission control lines; and a data driver configured to drive the data lines (Kim at Fig. 2),
each of the sub-pixels comprising: a first transistor having a first electrode connected via a first node to a first power supply voltage node configured to receive a first power supply voltage, a second electrode connected to a second node, and a gate electrode connected to a third node (Kim at Fig. 4, transistor M2);
a light emitting element connected between the second node and a second power supply voltage node configured to receive a second power supply voltage (Kim at Fig. 4, OLED);
a second transistor connected between a data line which is any one of the data lines and the third node, and having a gate electrode connected to a first sub-gate line which is any one of the gate lines (Kim at Fig. 4, transistor M1);
a first capacitor including a first electrode and a second electrode, wherein the first electrode is connected to the third node and the second node [electrode] is connected to the first node (Kim at Fig. 4, capacitor C1)…
a third capacitor including a first electrode and a second electrode, wherein the first electrode is connected to the third node (Kim at Fig. 4, capacitor C3).
Kim does not disclose that the second electrode of the third capacitor is connected to the second node.
Kim does not disclose a second capacitor including a first electrode and a second electrode, wherein the first electrode is connected to the third node and the second node [electrode] is connected to an initialization voltage node configured to receive an initialization voltage; and wherein the initialization voltage is different from the second power supply voltage.
However, Luis does disclose that the second electrode of the third capacitor is connected to the second node (Luis at Fig. 2B, capacitor Cst is connected to the source of transistor 220)
Luis also discloses a second capacitor including a first electrode and a second electrode, wherein the first electrode is connected to the third node and the second node [electrode] is connected to an initialization voltage node configured to receive an initialization voltage (Luis at Fig. 2B, capacitor 250 is connected between gate of transistor 220 and predetermined voltage SCM); and
wherein the initialization voltage is different from the second power supply voltage (Luis at ¶ [0050] discloses “In one embodiment, the absolute value of the level of the predetermined voltage S.sub.CM is greater than 0.”).
Kim discloses a base OLED display device upon which the claimed invention is an improvement. Luis discloses a comparable OLED display device which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to Kim the teachings of Luis for the predictable result of avoiding the problem of crosstalk (Luis at ¶ [0154]).
The combination of Kim and Luis results in wherein the third is commonly connected to the first transistor, the second transistor, a [the] first electrode of the first capacitor, a [the] first electrode of the second capacitor, and a [the] first electrode of the third capacitor (Kim at Fig. 4; Luis at Fig. 2B).
Kim discloses a base OLED display device upon which the claimed invention is an improvement. Luis discloses a comparable OLED display device which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to Kim the teachings of Luis for the predictable result of avoiding the problem of crosstalk (Luis at ¶ [0154]).
As to claim 12, the combination of Kim and Luis discloses the display device of claim 11, wherein each of the sub-pixels further comprises a third transistor connected between the first power supply voltage node and the first node and having a gate electrode connected to an emission control line which is any one of the emission control lines (Kim at Fig. 4, transistor M3).
As to claim 13, the combination of Kim and Luis discloses the display device of claim 12, wherein each of the sub-pixels further comprises a fourth transistor connected between the second node and the initialization voltage node and having a gate electrode which is connected to a second sub-gate line which is any one of the gate lines(Luis at Fig. 2B, transistor 230).6
As to claim 20, Kim discloses an electronic device, comprising a processor to provide image data; a display device to display an image based on the image data (; and wherein the display device, comprising: sub-pixels connected to data lines, gate lines, and emission control lines; a gate driver configured to drive the gate lines and the emission control lines; and a data driver configured to drive the data lines Kim at Fig. 2),
each of the sub-pixels comprising: a first transistor having a first electrode connected via a first node to a first power supply voltage node configured to receive a first power supply voltage, a second electrode connected to a second node, and a gate electrode connected to a third node (Kim at Fig. 4, transistor M2);
a light emitting element connected between the second node and a second power supply voltage node configured to receive a second power supply voltage (Kim at Fig. 4, OLED);
a second transistor connected between a data line which is any one of the data lines and the third node, and having a gate electrode connected to a first sub-gate line which is any one of the gate lines (Kim at Fig. 4, transistor M1);
a first capacitor including a first electrode and a second electrode, wherein the first electrode is connected to the third node and the second node [electrode] is connected to the first node (Kim at Fig. 4, capacitor C1)…
a third capacitor including a first electrode and a second electrode, wherein the first electrode is connected to the third node (Kim at Fig. 4, capacitor C3).
Kim does not disclose that the second electrode of the third capacitor is connected to the second node.
Kim does not disclose a second capacitor including a first electrode and a second electrode, wherein the first electrode is connected to the third node and the second node [electrode] is connected to an initialization voltage node configured to receive an initialization voltage; and wherein the initialization voltage is different from the second power supply voltage.
However, Luis does disclose that the second electrode of the third capacitor is connected to the second node (Luis at Fig. 2B, capacitor Cst is connected to the source of transistor 220)
Luis also discloses a second capacitor including a first electrode and a second electrode, wherein the first electrode is connected to the third node and the second node [electrode] is connected to an initialization voltage node configured to receive an initialization voltage (Luis at Fig. 2B, capacitor 250 is connected between gate of transistor 220 and predetermined voltage SCM); and
wherein the initialization voltage is different from the second power supply voltage (Luis at ¶ [0050] discloses “In one embodiment, the absolute value of the level of the predetermined voltage S.sub.CM is greater than 0.”).
Kim discloses a base OLED display device upon which the claimed invention is an improvement. Luis discloses a comparable OLED display device which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to Kim the teachings of Luis for the predictable result of avoiding the problem of crosstalk (Luis at ¶ [0154]).
The combination of Kim and Luis results in wherein the third is commonly connected to the first transistor, the second transistor, a [the] first electrode of the first capacitor, a [the] first electrode of the second capacitor, and a [the] first electrode of the third capacitor (Kim at Fig. 4; Luis at Fig. 2B).
Kim discloses a base OLED display device upon which the claimed invention is an improvement. Luis discloses a comparable OLED display device which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to Kim the teachings of Luis for the predictable result of avoiding the problem of crosstalk (Luis at ¶ [0154]).
Claims 4-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kim and Luis as applied to claim 3 above, and further in view of Yoon (US 2018/0005576 A1, Published January 4, 2018).
As to claim 4, the combination of Kim and Luis discloses the sub-pixel of claim 3, wherein the first transistor, the second transistor and the third transistor are P-type transistors (Kim at Fig. 4).
The combination does not disclose that the fourth transistor is an N-type transistor.
However, Yoon does disclose that the fourth transistor is an N-type transistor (Yoon at Figs. 9, 11, 16, in particular)
The combination of Kim and Luis discloses a base OLED display device upon which the claimed invention is an improvement. Yoon discloses a comparable OLED display device which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to the combination of Kim and Luis the teachings of Yoon for the predictable result of suppressing a flicker phenomenon (Yoon at ¶ [0014]).
As to claim 5, the combination of Kim, Luis, and Yoon discloses the sub-pixel of claim 4, wherein each of the first to fourth transistors includes a body electrode, and the body electrode of each of the first to third transistors are configured to receive the first power supply voltage (Kim at Fig. 4), and
the body electrode of the fourth transistor is configured to receive the initialization voltage (Yoon at Fig. 11).
As to claim 6, the combination of Kim, Luis, and Yoon discloses the sub-pixel of claim 3, wherein one horizontal period is divided into a first period, a second period, and a third period, the second transistor is turned on during the first period and the second period, the fourth transistor is turned on during the first period to the third periods, and the third transistor is turned off during the second period (Kim at Figs. 4-5).
As to claim 7, the combination of Kim, Luis, and Yoon discloses the sub-pixel of claim 6, wherein the data line is configured to receive a voltage of a data signal during the first period to the third period (Kim at Figs. 3-5).
As to claim 8, the combination of Kim, Luis, and Yoon discloses the sub-pixel of claim 6, wherein the third transistor is configured to be turned off during the first period (Kim at Figs. 4-5).
As to claim 9, the combination of Kim, Luis, and Yoon discloses the sub-pixel of claim 3, wherein the initialization voltage is a voltage by which the light emitting element is configured to be turned off based on the voltage being supplied to the light emitting element (Kim at Fig. 4).
As to claim 10, the combination of Kim, Luis, and Yoon discloses the sub-pixel of claim 2, further comprising: a fourth transistor connected between the second node and an auxiliary initialization voltage node configured to receive an auxiliary initialization voltage, and having a gate electrode connected to a second sub-gate line, wherein the auxiliary initialization voltage is a voltage which is different from the initialization voltage (Yoon at Figs. 9, 11, 16, in particular).
The combination of Kim and Luis discloses a base OLED display device upon which the claimed invention is an improvement. Yoon discloses a comparable OLED display device which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to the combination of Kim and Luis the teachings of Yoon for the predictable result of suppressing a flicker phenomenon (Yoon at ¶ [0014]).
Claims 14-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim and Luis as applied to claim 12 above, and further in view of Yoon (US 2018/0005576 A1, Published January 4, 2018).
As to claim 14, the combination of Kim and Luis discloses the display device of claim 13, wherein the first transistor, the second transistor and the third transistor are P-type transistors (Kim at Fig. 4).
The combination does not disclose the fourth transistor is an N-type transistor.
However, Yoon does disclose the fourth transistor is an N-type transistor (Yoon at Figs. 9, 11, 16, in particular)
The combination of Kim and Luis discloses a base OLED display device upon which the claimed invention is an improvement. Yoon discloses a comparable OLED display device which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to the combination of Kim and Luis the teachings of Yoon for the predictable result of suppressing a flicker phenomenon (Yoon at ¶ [0014]).
As to claim 15, the combination of Kim, Luis, and Yoon discloses the display device of claim 14, wherein each of the first to fourth transistors includes a body electrode, and the body electrode of each of the first to third transistors are configured to receive the first power supply voltage (Kim at Fig. 4), and
the body electrode of the fourth transistor is configured to receive the initialization voltage (Yoon at Fig. 11).
As to claim 16, the combination of Kim, Luis, and Yoon discloses the display device of claim 13, wherein one horizontal period is divided into a first period, a second period, and a third period, and the gate driver is configured to supply a first scan signal with a gate-on voltage to the first sub-gate line during the first period and the second period, to supply a second scan signal with a gate-on voltage to the second sub-gate line during the first period to the third period, and to supply an emission control signal with a gate-off voltage to the emission control line during the second period (Kim at Figs. 4-5).
As to claim 17, the combination of Kim, Luis, and Yoon discloses the display device of claim 16, wherein the data driver is configured to supply a voltage of a data signal to the data line during the first period to the third period (Kim at Figs. 3-5).
As to claim 18, the combination of Kim, Luis, and Yoon discloses the display device of claim 16, wherein the gate driver is further configured to supply the emission control signal to the emission control line during the first period (Kim at Figs. 4-5).
As to claim 19, the combination of Kim, Luis, and Yoon discloses the display device of claim 12, wherein each of the sub-pixels further comprises a fourth transistor connected between the second node and an auxiliary initialization voltage node to which an auxiliary initialization voltage is supplied and having a gate electrode which is connected to a second sub-gate line which is any one of the gate lines, and the auxiliary initialization voltage is a voltage which is different from the initialization voltage (Yoon at Figs. 9, 11, 16, in particular).
Kim discloses a base OLED display device upon which the claimed invention is an improvement. Yoon discloses a comparable OLED display device which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to Kim the teachings of Yoon for the predictable result of suppressing a flicker phenomenon (Yoon at ¶ [0014]).
The combination of Kim and Luis discloses a base OLED display device upon which the claimed invention is an improvement. Yoon discloses a comparable OLED display device which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to the combination of Kim and Luis the teachings of Yoon for the predictable result of suppressing a flicker phenomenon (Yoon at ¶ [0014]).
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Luis (US 2018/0062105 A1, Published March 1, 2018) is made of record for its relevance to claims 1, 11, and 20 by its disclosure of an auxiliary capacitor 250 and predetermined voltage SCM at Fig. 2B:
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Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Sanjiv D Patel whose telephone number is (571)270-5731. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Boddie can be reached at 571-272-0666. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Sanjiv D. Patel/Primary Examiner, Art Unit 2625
06/14/2026
1 See also Kim at Fig. 4.
2 See also Kim at Fig. 4
3 See also Kim at Fig. 4
4 See also Kim at Fig. 4
5 See also Yoon at Fig. 14, transistor T2.
6 See also Yoon at Fig. 14, transistor T2.
Prosecution Insights