DETAILED ACTION
Claims 1-20 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy of CN 202410749437.9 was electronically retrieved by the USPTO on May 24, 2025.
Specification
The title of the invention is not sufficiently descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The disclosure is objected to because of the following informalities:
In paragraph 57, both instances of “write data from the…memory” are grammatically incorrect and must be reworded.
In paragraphs 108 and 115, all four instances of “their any…” are grammatically incorrect and must be reworded.
Appropriate correction is required.
Drawings
The drawings are objected to because of the following minor informalities:
In FIGs.1-8, “network” is misspelled.
All FIGs are objected to for failing to comply with 37 CFR 1.84(a)(1) and 37 CFR 1.84(L), which requires that all drawings be made by a process which will give them satisfactory reproduction characteristics. Every line, number, and letter must be durable, clean, solid black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined. The weight of all lines and letters must be heavy enough to permit adequate reproduction. This requirement applies to all lines however fine, to shading, and to lines representing cut surfaces in sectional views. The examiner asserts that the quality of the FIGs, which include non-uniform and pixelated lines/text, is inadequate.
FIGs.2 and 5 are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference characters not mentioned in the description: 200 and 500.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) and/or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 1 is objected to because of the following informalities:
In line 2, insert a colon after “wherein”.
In line 6, either replace both instances of “is” with --being-- or start new paragraphs after each comma.
Claim 6 is objected to because of the following informalities:
Lines 2-3 set forth switching a switch through a switch. This is grammatically incorrect and must be reworded.
Claim 7 is objected to because of the following informalities:
In line 1, please clarify what is being applied to the second processor. Is it the method? Or is it the model?
Append line 4 to the end of line 3.
Claim 8 is objected to because of the following informalities:
Line 3 sets forth switching a switch through a switch. This is grammatically incorrect and must be reworded.
Claim 9 is objected to because of the following informalities:
In the 2nd to last line, delete the comma.
Claim 10 is objected to because of the following informalities:
Line 3 sets forth switching a switch through a switch. This is grammatically incorrect and must be reworded.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of MPEP 2111.04(II):
“The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met.”
“The broadest reasonable interpretation of a system (or apparatus or product) claim having structure that performs a function, which only needs to occur if a condition precedent is met, requires structure for performing the function should the condition occur. The system claim interpretation differs from a method claim interpretation because the claimed structure must be present in the system regardless of whether the condition is met and the function is actually performed.”
Regarding claim 8, and based on the description in paragraphs 92-93, the switching is not required to be performed if the function of communication of line 4 is enabled. It is recommended that applicant claim an initial step of --determining that a function of data communication with the target memory is disabled--. Then, applicant could claim
--switching…in response to the determining…--. These amendments would then remove the contingency and require the switching to occur.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5-6 and 9-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claims recite the following limitations for which there is a lack of antecedent basis:
In claim 5, “the data communication with the target memory”, because this could refer to the communication in claim 1, last paragraph, or to the communication in claim 2, lines 1-2.
In claim 6, “the data communication with the target memory” for similar reasoning.
In claim 9, lines 4 and 7, both instances of “the second function”.
In claim 10, line 2, “the processor”. Please amend to clarify whether applicant is referring to the processor of claim 9, line 2, or to the first processor.
In claim 10, last line, “the second processor”.
In claim 11, “the processor”.
In claim 13, both instances of “the scale”.
In claims 17-19, each instance of “the second processor”.
Claims 6 and 10-20 are rejected due to its dependence on an indefinite claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 7-9, and 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ahn et al. (US 2021/0191728) in view of the examiner’s taking of Official Notice.
Referring to claim 1, Ahn has taught a terminal device (FIG.1a, device 100), comprising:
a first processor (FIG.1a, CPU 110), a second processor (FIG.1a, accelerator 120) and a target memory (e.g. FIG.1a, memory 140; FIG.3, 329; FIG.5, 530; FIG.6, 630) that are communicatively connected; wherein
the first processor is configured to execute a first function (a CPU executes a CPU function); the second processor is configured to perform data communication with the first processor and execute a second function based on data obtained from the communication (see paragraph 39 and FIGs.2-3. Commands are communicated from the CPU to the accelerator’s command queue), the second function is a data processing function based on a model (from paragraph 11, the accelerator accelerates operations of a neural network model (and could include convolution operations (FIG.3, Conv))), and the second function is different from the first function (CPU and neural network accelerator functions are different. FIG.2 shows examples of different functions performed); and the target memory is configured to perform data communication with the second processor and store data obtained by running the second processor (the target memory includes at least one of input data obtained when a memory read or convolution occurs (e.g. commands 1-2 in FIG.6), or a result of acceleration (the result stored in FIG.3, 329, and later to SSD or memory (FIGs.5-6))).
Ahn has not taught that the second processor is a computing-in-memory processor. However, Official Notice is taken that processor-in-memory systems, including ones to implement neural network models, were well-known in the art before applicant's invention. A processor implemented in a memory device performs operations on memory data without having to send the data to an external processor. Eliminating this traffic could reduce power consumption and latency. As a result, since Ahn already teaches the accelerator closely working with memory, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Ahn such that the second processor is a computing-in-memory processor.
Referring to claim 4, Ahn, as modified, has taught the terminal device according to claim 1, wherein the second processor is configured to:
receive a model processing instruction sent by the first processor (see FIG.2, 220, and the received commands in FIGs.3-6);
read model startup data from the target memory based on the model processing instruction (see FIGs.3-6. Data is read from target memory based on the instructions);
run a model based on the model processing instruction and the model startup data (again, from paragraph 11, a neural network is executed based on the commands and data), to execute the second function, and generate a model output result (e.g. FIGs.3-6, “result”); and
send the model output result to the first processor (see paragraph 39. The result is ultimately sent to the first processor).
Ahn has not taught that the model is a generative model. However, Official Notice is taken that generative models were well-known in the art before applicant's invention. Such constitute a sub-field of artificial intelligence that can be used to generate images, music, software code, and text for purposes of conversation (e.g. chatbot). As a result, in order to realize these capabilities for interaction, creativity, etc., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Ahn such that the model is a generative model.
Claim 7 is rejected for similar reasoning as claims 1 and 4.
Referring to claim 8, Ahn, as modified, has taught the method according to claim 7, wherein reading model startup data from the target memory based on the model processing instruction comprises: (this limitation is contingent and not required when the communication is enabled)(communication must be enabled between the second processor and memory if access is to occur); and reading the model startup data from the target memory based on the model processing instruction in response to determining that the function of the data communication with the target memory is enabled (as long as access is permitted, the instructions will cause the second processor to read startup data from memory).
Claim 9 is mostly rejected for similar reasoning as claims 1 and 4. Ahn has further taught a non-transitory computer-readable storage medium, storing a computer program, wherein the computer program, when executed by a processor, causes the processor to perform the claimed steps (paragraph 101).
Referring to claim 11, Ahn, as modified, has taught the non-transitory computer-readable storage medium of claim 9, wherein the computer program further causes the processor to: read the model startup data from the target memory based on the model processing instruction in response to determining that the function of the data communication with the target memory is enabled (as long as the reading is allowed to occur (there is nothing causing it to be denied), it is determined that the communication is enabled, and the communication will occur).
Referring to claim 12, Ahn, as modified, has taught the non-transitory computer-readable storage medium of claim 9, wherein the first function is a function of a first model (a first function would be transmitting commands to the accelerator (FIG.2, 220). The first model is thus command transmission).
Referring to claim 13, Ahn, as modified, has taught the non-transitory computer-readable storage medium of claim 12, wherein the scale of the first model is smaller than the scale of the generative model (a model to transmit commands is deemed smaller than the neural network model which involves at least reading commands, retrieving data, performing various processor, and storing results).
Referring to claim 14, Ahn, as modified, has taught the non-transitory computer-readable storage medium of claim 12, wherein the first function is an operating system function (see paragraph 98, where a processor runs an operation system to perform the operations described. The operations include the command transmission).
Referring to claim 15, Ahn, as modified, has taught the non-transitory computer-readable storage medium of claim 12, wherein the first function is an application function of an application (paragraph 98; an applicant running on an OS may perform the operations described). Ahn has not taught that the applicant is a third-party application. However, Official Notice is taken that such applications were well-known in the art before applicant's invention. Relying on a third-party application could reduce in-house development costs, debugging, maintenance, etc. As a result, in order to use an already-existing and established application as opposed to programming a proprietary application from scratch and subsequently maintaining it, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the application to be a third-party application.
Referring to claim 16, Ahn, as modified, has taught the non-transitory computer-readable storage medium of claim 12, but has not taught wherein the first function is one of an image processing function, a display function, a sensor control function, an audio control function, a camera control function and a message broadcasting function. However, Official Notice is taken that such functions were well-known in the art before applicant's invention. These functions are very broad and could encompass many different functions. For instance, it is known to connect a CPU to a display so as to output data for viewing. The processor may have integrated graphics to control the display, in which case, the CPU executes a display function to provide a visual for a user. Even without integrated graphics (e.g. perhaps a dedicated GPU is provided), the CPU is still known to send data to the GPU, and this sending, and processing related thereto would be a display function. Similar reasoning applies to audio functions. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Ahn such that the first function is one of an image processing function, a display function, a sensor control function, an audio control function, a camera control function and a message broadcasting function.
Referring to claim 17, Ahn, as modified, has taught the non-transitory computer-readable storage medium of claim 9, wherein the first processor, the second processor and the target memory are communicatively connected (again, see FIGs.1a and 3-6. Everything in the system is coupled (directly and/or indirectly)).
Claims 18-20 are rejected for similar reasoning set forth in the rejections of claims 1, 1, and 2, respectively.
Claims 2-3, 5-6, and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Ahn in view of the examiner’s taking of Official Notice and Evoy et al. (US 5,953,741).
Referring to claim 2, Ahn, as modified, has taught the terminal device according to claim 1, wherein the target memory is further configured to perform data communication with the first processor and store data obtained by running the first processor (from paragraph 39, the first processor, when running, may obtain result data stored in the target memory);
While both processors may read/write to memory (e.g. see FIG.1), Ahn has not taught that the terminal device further comprises a bus switch, and the bus switch is communicatively connected to the first processor, the second processor and the target memory, and is configured to switch the target memory to perform the data communication with the first processor or switch the target memory to perform the data communication with the second processor. However, Evoy has taught a similar system where a processor and coprocessor share a memory (FIG.2, 28) via a shared bus (FIG.1, 21). From column 7, lines 56-61, “Co-processor interface block 54 also is coupled to a bus arbitrator 44 which handles arbitration of bus 21 between processors 40 and 50, as well as any other devices coupled to the bus (not shown), also in a manner known in the art. In general, only one device is given control of bus 21 at a time…” (other locations discuss switching bus/memory access between processors 40 and 50). This allows for a shared bus and even shared memory ports, thereby reducing hardware. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Ahn such that the terminal device further comprises a bus switch, and the bus switch is communicatively connected to the first processor, the second processor and the target memory, and is configured to switch the target memory to perform the data communication with the first processor or switch the target memory to perform the data communication with the second processor.
Referring to claim 3, Ahn, as modified, has taught the terminal device according to claim 2, and, under a first interpretation, wherein the bus switch is integrated into the first processor, the second processor or the target memory (from column 7, lines 41-42, the coprocessor 50 asserts control through the arbitrator. Thus, the switch signal comes from the coprocessor, in which case, it can be said that the bus switch is at least partially integrated into the second processor. From column 7, lines 60-65, each processor may issue requests to switch the bus to it for use; thus, it can be said that the bus switch is at least partially integrated into both processors that are making these requests). Under a second interpretation, where the arbiter 44 is deemed the switch, this is not shown as being integrated into one of the processors or the target memory. However, integrating components is deemed a routine expedient, not a patentable distinction (see MPEP 2144.04, including section (V)(B)) Since there is no demonstration of criticality of the location of this switch, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Ahn such that the bus switch is integrated into the first processor, the second processor or the target memory.
Referring to claim 5, Ahn, as modified, has taught the terminal device according to claim 2, wherein the second processor is configured to:
receive a model processing instruction sent by the first processor (see FIG.2, 220, and the received commands in FIGs.3-6);
read model startup data from the target memory based on the model processing instruction in response to determining that a function of the data communication with the target memory is enabled (see FIGs.3-6. Data is read from target memory based on the instructions. And, as modified, data can only be read when communication is enabled between the second processor and memory (as decided by the arbiter));
run a model based on the model processing instruction and the model startup data (again, from paragraph 11, a neural network is executed based on the commands and data), to execute the second function, and generate a model output result (e.g. FIGs.3-6, “result”); and
send the model output result to the first processor (see paragraph 39. The result is ultimately sent to the first processor).
Ahn has not taught that the model is a generative model. However, Official Notice is taken that generative models were well-known in the art before applicant's invention. Such constitute a sub-field of artificial intelligence that can be used to generate images, music, software code, and text for purposes of conversation (e.g. chatbot). As a result, in order to realize these capabilities for interaction, creativity, etc., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Ahn such that the model is a generative model.
Referring to claim 6, Ahn, as modified, has taught the terminal device according to claim 5, wherein the second processor is further configured to: after receiving the model processing instruction sent by the first processor, switch a communication switch of the target memory through the bus switch in response to determining that the function of the data communication with the target memory is disabled (this is how the modified system would operate, with each processor making requests to access the memory. If the accelerator needs to start reading data from memory for processing, a request to an arbitrator is made. If the memory is currently used by the first processor, then the second processor is locked out (communication is disabled), and communication must be enabled before it can read the data it needs), and enable a function of communication of the second processor with the target memory (the enabling will eventually occur when the request is granted).
Claim 8, when considering all limitations, is alternatively rejected for similar reasoning as claims 5-6.
Claim 10 is rejected for similar reasoning as claim 6.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Xu (US 2020/0050476) has taught a CPU coupled to an AI chip that generates a result made accessible to the CPU. The CPU sends code to the AI chip to execute a neural network model.
Henry (US 2017/0103307) has taught a processor with a neural network unit (NNU). The processor writes instructions to the NNU. The NNU receives data from memory, and writes a result to the same memory, which is also accessible by the processor.
Lee (US 2024/0272949) has taught a processor connected to a neural network accelerator and the interface therebetween.
Park (US 2025/0225096) has taught a CPU connected to an NPU, where the CPU includes an arbiter to allow the CPU or NPU to access a cache memory.
Ren (WO 2023/123648) has taught a CPU/coprocessor interface through which instructions are transmitted. An MCR instruction configures internal registers of the coprocessor and a CDP instruction initiates convolution operations.
Sumbul (US 2019/0043560) has taught compute-in-memory for MAC operations for neural network processing.
Park (US 2002/0133689) has taught a processor/coprocessor configuration where the coprocessor is activated by the processor upon pre-decoding a coprocessor instruction and the remaining coprocessor code is fetched by the coprocessor from coprocessor memory.
Wu has taught “Design of Neural Network Accelerator Based on In-Memory Computing Theory” with a CPU coupled to a compute-in-memory neural accelerator.
Imani has taught “RAPIDNN: In-Memory Deep Neural Network Acceleration Framework”.
Wikipedia has taught the basics of “In-memory processing”.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183
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