DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 12, 14-15 and 17-19 is/are rejected under 35 U.S.C. 102(a)(1) as being antiicpated by Duvnjak (US 20220200459).
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With respect to claim 12, Duvnjak (US 20220200459) discloses an electronic component comprising: a ground terminal (109) , a drain terminal (at 111), an input terminal (at Vin i.e. 102), and a current sense terminal (at ISNS) at an exterior surface of the electronic component (external to electrical component fig. 1A); a power circuit (108) arranged to conduct a current (ISW) between the ground terminal (109) and the drain terminal (at 111); a logic circuit (130 and 132) arranged to detect a magnitude of the current (current through ISW) and to generate a signal at the current sense terminal (ISNS) that is proportional to the current (ISW); and a driver circuit (134) arranged to control the current according to an input signal (Vin) at the input terminal (controls based in Vin).
With respect to claim 14, Duvnjak discloses the electronic component of claim 12, wherein the logic circuit (130 and 132) is arranged to disable (disable is interpreted as sending signal to turn the switch off) the driver circuit (134) in response to the current exceeding a predetermined threshold (see [0035]: “The drive signal generator and drive strength control 132 is also configured to receive the current sense signal ISNS 126 representative of the switch current ISW 116 of power switch S1 110 and the feedback signal FB 124 representative of the output voltage V.sub.O 121. The drive signal generator and drive strength control 132 determines when to turn ON and turn OFF the power switch S1 110 and outputs the drive signal DR 140 to control the switching of the power switch S1 110.”) .
With respect to claim 15, Duvnjak discloses the electronic component of claim 12, wherein the logic circuit (130 and 132) is arranged to disable the driver circuit (134) in response to a temperature of the power circuit exceeding a predetermined temperature (See: [0022]: The time for the power switch to transition from an OFF state to an ON state is referred to as the turn-on time. Switching (otherwise also referred to as crossover) losses occur during this transition time and shorter turn-on times generally correspond with reduced switching losses and temperature. ).
With respect to claim 17, Duvnjak discloses the electronic component of claim 12, wherein a spacing between the drain terminal (at 111) and the input terminal (102) is greater than a spacing between the input terminal (102) and the current sense terminal (at ISNS i.e. terminal at VD)).
With respect to claim 18, Duvnjak discloses the electronic component of claim 12, wherein at least a part of the power circuit is formed on a gallium nitride (GaN) substrate (see [0027], “ the first cascode switch 112 may be a high-voltage GaN transistor.”).
With respect to claim 19, Duvnjak discloses the electronic component of claim 14, wherein the logic circuit is coupled to an external circuit (output sense circuit (not shown) see [0030]: “It should be appreciated that an output sense circuit (not shown) may provide the feedback signal FB 124 to controller 122.”) and wherein the predetermined threshold is at least partially determined by the external circuit.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Duvnjak.
With respect to claim 13, Duvnjak discloses the electronic component of claim 12, further comprising a power supply terminal (VDD) coupled to the driver circuit (134 shown in fig. 5), the power supply terminal arranged to receive power but fails to explicitly state the power supply terminal is coupled to the logic (130 and 132).
It is well known that operational amplifiers (such as 248) are powered externally. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to use the power circuit Vdd to power the op amp in 248, for the purpose of powering the device with a readily available source.
Allowable Subject Matter
Claims 16 and 20] objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 16, the prior art of record fails to explicitly disclose wherein the input signal is a pulse width modulated (PWM) signal.
With respect to claim 20, the prior art of record fails to explicitly disclose wherein the external circuit comprises a resistor, and wherein the threshold current is at least partially based on a resistance of the resistor.
Claims 1-11 are allowed.
The following is an examiner’s statement of reasons for allowance:
With respect to claim 1, the closest reference Knogden (20160134196) fails to explicitly suggest or disclose a power supply terminal and a current sense terminal at an exterior surface of the electronic component; a first semiconductor device attached to the base and including a gate, a source and a drain, the first semiconductor device arranged to conduct a current between the source and the drain, wherein the source is coupled to the ground terminal ,wherein the drain is coupled to the drain terminal ; a second semiconductor device attached to the base and arranged to receive power from the power supply terminal, the second semiconductor device including: a logic circuit arranged to detect a magnitude of the current and to generate a signal at the current sense terminal that is proportional to the current; a driver circuit arranged to control the current according to an input signal at the input terminal; and an electrically insulative encapsulant at least partially encapsulating the base, the first semiconductor device and the second semiconductor device.
Claims 2-11 are allowable on the basis of their dependence on claim 1.
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/KHAREEM E ALMO/Examiner, Art Unit 2836
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