Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This Office Action is in response to the filing with the office dated 04/05/2026.
Claims 1-6, 8-11, 13, 15-20 have been amended. Claims 1, 8 and 15 are independent claims. Claims 1-20 are presented in this office action.
Priority
3. Applicant’s claim for the benefit of a prior-filed provisional Application No. 63/704,279 filed on 10/07/2024 is acknowledged by the examiner.
Information Disclosure Statement
4. The information disclosure statement (IDS) submitted on 04/16/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to amendment/arguments
5. Applicant’s arguments with respect to the rejection of claims under 35 U.S.C. § 101 as the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more, have been fully considered. However, Examiner respectfully disagrees with the applicant’s argument. See response to arguments section. The rejection has been maintained.
6. Applicant’s arguments with respect to the rejection of claims under 35 U.S.C. § 102 (a)(i) and 103(a) have been fully considered but are moot because the arguments are directed towards amended claims, thus necessitated the new ground of rejection as presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Response to 101 rejection
7. Applicants arguments regarding 101 rejection on page 11 recites “Even assuming arguendo that it could be determined that the claims somehow do explicitly recite a judicial exception, each of the claims integrates such recitation into a practical application and, therefore, should be deemed to be not "directed to" the patent- ineligible judicial exception in accordance with the second prong of the Revised Step 2A. Specifically, claim 1, as amended, recites concrete technical operations that go beyond any alleged abstract idea. Claim 1 now recites "responsive to advancing the tail pointer, at least one of: providing entries of the second segment to one or more consumer processes of the plurality of processes, or deallocating memory associated with entries of the second segment." These are concrete operations that improve management of computer memory for parallel processing queues. Accordingly, applicant respectfully asserts that any alleged abstract idea is integrated into a practical application” and “Even assuming arguendo that it could be determined that the claims somehow are not integrated into a practical application under the second prong of Step 2A, the claims add significantly more than the judicial exception under Step 2B. As discussed above, the claims recite specific operations for advancing a tail pointer based on a counter threshold and, in response, providing entries to consumer processes or deallocating memory. Applicant respectfully asserts that these operations, in context as claimed, are not well- understood, routine, or conventional. Accordingly, Applicant respectfully requests that the rejections of claims 1-20 under 35 U.S.C. § 101 be withdrawn”
Examiner respectfully disagrees as the amended claim limitation "responsive to advancing the tail pointer….” under broadest reasonable interpretation, covers performance of the limitation in the mind. There is, nothing in the claim element that precludes the steps from practically being performed by a human mentally or with pen and paper. This limitations, at the high level of generality as drafted, would encompass a user to receive a segment from a queue and in response to determining that the number of data elements are processed/ write/ read having a link entry at the end of the segment indicates that the processing of one segment is complete and a new segment is processed from the queue. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Claim 1 does not recite limitations that amount to significantly more than the abstract idea. The limitations are steps involving processes that can be practically performed by a human with the aid of pen and paper, or as explained above, using a computer as a tool to perform the concept. These limitations do not improve the functioning of a computer, improve the technology, apply the abstract idea to a particular machine, effect a transformation, nor provide meaningful limitations beyond linking the abstract idea to computer technology. They do not recite specific details that amount to significantly more than the abstract idea or providing meaningful limits on the abstract idea. For at least these reasons, claims 1, 8 and 15 are nonstatutory because they are directed to a judicial exception without significantly more.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
8. Claims 1-20 are rejected under 35 U.S.C. 101 because the instant application is directed to non-patentable subject matter. Specifically, the claims are directed toward at least one judicial exception without reciting additional elements that amount to significantly more than the judicial exception. The rationale for this determination is in accordance with the guidelines of USPTO, applies to all statutory categories, and is explained in detail below.
Pursuant to Step 2A, part 1, claims are analyzed to determine whether they are directed to an abstract idea. Under the 2019 PEG, claims are deemed to be directed to an abstract idea if they fall within one of the enumerated categories of (a) mathematical concepts, (b) certain methods of organizing human activity, and (c) mental processes. Here, claim 1 are directed to an abstract idea categorized under mental processes. Courts consider a mental process if it “can be performed in the human mind, or by a human using a pen and paper.” MPEP 2016(a)(2)(III). Courts also consider a mental process as one that can be performed in the human mind and is merely using a computer as a tool to perform the concept. MPEP 2016(a)(2)(III)(C)(3). Claim 1 recites a mental process because the recited steps recite the actions “providing…”, “modifying….” but is recited at a high level of generality that merely used computers as a tool to perform the processes. See MPEP 2106(a)(2)(III). For example, claim 1 recites limitations of “providing first entry …”, “providing second entry …”, “ modifying the data structure with a first counter….”, “ modifying the data structure with a second counter….”. A system, memory, processor are recited at a high level of generality and do not place meaningful limits on the abstract idea. These limitations are essentially steps of manipulating data at a high level of generality, which can be performed by a person using a computer as a tool. There is, nothing in the claim element that precludes the steps from practically being performed by a human mentally or with pen and paper.
Pursuant to Step 2A, part 2, claims are analyzed to determine whether the recited abstract idea is integrated into a practical application. In this case, as explained above, claim 1 merely recite a mental process. These limitations describe “providing first entry …”, “providing second entry …”, “ modifying the data structure with a first counter….”, “ modifying the data structure with a second counter….”, "responsive to advancing the tail pointer, at least one of: providing entries of the second segment to one or more consumer processes of the plurality of processes, or deallocating memory associated with entries of the second segment.". While claim 1 recites additional components in the form of a system, memory and processor, these components are recited at a high level of generality, which do not add meaningful limits on the recited abstract idea to integrate it into a practical application by providing an improvement to the functioning of a computer or technology, implementing the abstract idea with a particular machine or manufacture that is integral to the claim, effecting a transformation or reduction of a particular article to a different state or thing, nor applying the abstract idea in some meaningful way beyond linking its use to computer technology. See 2019 PEG. There are ono additional elements. These limitations, at the high level of generality as drafted, would encompass a user to provide entries to a queue and based on the queue entries, modifying the data structure by incrementing the counter, which is mentally performable in mind or with use of pen and paper as an evaluation or judgement. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claims 1, 8 and 15 recite an abstract idea.
Since claims 1, 8 and 15 are directed to an abstract idea categorized as a mental process and does not integrate the judicial exception into a practical application, claims 1, 8 and 15 is directed to a judicial exception.
Pursuant to Step 2B, claims are analyzed to determine whether they recite significantly more than the abstract idea. In other words, it is determined whether the claims provide an inventive concept. In this case, claim 1 does not recite limitations that amount to significantly more than the abstract idea. The limitations are steps involving processes that can be practically performed by a human with the aid of pen and paper, or as explained above, using a computer as a tool to perform the concept. These limitations do not improve the functioning of a computer, improve the technology, apply the abstract idea to a particular machine, effect a transformation, nor provide meaningful limitations beyond linking the abstract idea to computer technology. They do not recite specific details that amount to significantly more than the abstract idea or providing meaningful limits on the abstract idea. For at least these reasons, claims 1, 8 and 15 are nonstatutory because they are directed to a judicial exception without significantly more.
Claims 2, 9 , 16 depends on claims 1, 8, 15 and therefore recites the same abstract idea. Pursuant to step 2A, part 2, claims 2, 9 , 16 recites “ first entry is in a first segment of the plurality of segments; the first counter is associated with the first segment of the plurality of segments; the second entry is in a second segment of the plurality of segments; and the second counter is associated with the second segment of the plurality of segments”. Thes limitation do not integrate the abstract idea into a practical application because the additional limitation merely describes entries and counters associated with plurality of segments. Therefore, these additional limitations do not integrate the abstract idea into a practical application. The additional limitations do not amount to significantly more than the abstract idea because the limitations are not recited in a manner that provides improvements to the functioning of a computer or any other technology or technical field.
Claims 3, 4, 10, 11, 17, 18 depends on claim 1, 8, 15 and therefore recites the same abstract idea. and therefore recites the same abstract idea. claims 3, 4, 10, 11, 17, 18 recites “modifying the tail pointer of the queue based on the data structure associated with the queue based on a criteria ”, “determining that a head pointer of the queue and the tail pointer point to a same segment of the queue…”. These limitations are steps involving processes that can be practically performed by a human with the aid of pen and paper, or as explained above, using a computer as a tool to perform the concept. These limitations do not improve the functioning of a computer, improve the technology, apply the abstract idea to a particular machine, effect a transformation, nor provide meaningful limitations beyond linking the abstract idea to computer technology. They do not recite specific details that amount to significantly more than the abstract idea or providing meaningful limits on the abstract idea.
Claims 5, 6, 7 12, 13, 14, 19, 20 depends on claim 1, 8, 15 and therefore recites the same abstract idea. claims5, 6, 7 12, 13, 14, 19, 20 recites “first section of the plurality of sections comprises a tail indicator bit, one or more tail address bits, the first counter, and the second counter”, “he first process is a producer process”, the first counter and the second counter each have a guard bit to indicate whether the threshold criterion has been satisfied.” These limitations are steps involving processes that can be practically performed by a human with the aid of pen and paper, or as explained above, using a computer as a tool to perform the concept. These limitations do not improve the functioning of a computer, improve the technology, apply the abstract idea to a particular machine, effect a transformation, nor provide meaningful limitations beyond linking the abstract idea to computer technology. They do not recite specific details that amount to significantly more than the abstract idea or providing meaningful limits on the abstract idea.
Claim Rejections - 35 U.S.C. § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. Claims 1- 20 are rejected under 35 U.S.C. 103 as being unpatentable over Svennebring; Jonas (US 20220043687 A1) in view of Regache; Pascal (US 5873089 A).
Regarding independent claim 1, Svennebring; Jonas (US 20220043687 A1) teaches, a method of managing entries in a queue that comprises a plurality of segments and is shared by a plurality of processes (Paragraph [0061]), the method comprising: providing a first entry of the queue to a first process of the plurality of processes (Fig. 1, Paragraph [0030] discloses, multi-producer multi-consumer queues (Based on specification [0121] first process can be producer process or consumer process) and, a second entry of the queue to a second process of the plurality of processes (Fig. 1, Paragraph [0030] discloses, multi-producer multi-consumer queues ( Based on specification [0121] first process can be producer process or consumer process);
responsive to receiving a first signal from the first process (Paragraph [0042] discloses, in response to receiving a signal from the first process/ producer to indicate that the circular queue is not full enqueuing values in the circular queue (Examiner interprets first process as producer circuitry)), modifying one or more sections of a data structure associated with the queue (Paragraph [0076] updating the producer index for the new element added in the queue. Also see [0038]), wherein each section of the data structure comprises one or more counters each associated with a segment of the plurality of segments (Paragraph [0076] discloses, plurality of sections, which is total number of elements in a segment and is incremented based on the total number of elements (Examiner interprets sections as elements), and wherein modifying the data structure associated with the queue for the first entry comprises incrementing a first counter associated with a first segment of the plurality of segments (Paragraph [0064] discloses, modifying the data structure by incrementing/ adding the values from the first entry of producer circuitry to the total length of the elements in a segment by enqueue process. Also see [0058],[0059] discloses, incrementing the segment counter associated with plurality of segments);
responsive to receiving a second signal from the second process (Paragraph [0049] discloses, in response to receiving a signal from the second process/ consumer to remove/ dequeue the value from the circular queue (Examiner interprets second process as consumer circuitry)), modifying the data structure associated with the queueof segments (Paragraph [0064] discloses, modifying the data structure by incrementing/ the values from the second entry to the total length of the elements in a segment by dequeue process);
Svennebring et al fails to explicitly teach, advancing a tail pointer of the queue from a first value to a second value based on an indication that each process operating on a respective entry within the second segment has completed use of the respective entry, and wherein the first value is associated with a beginning of the second segment and the second value is associated with an end of the second segment; and
Regache; Pascal (US 5873089 A) teaches, advancing a tail pointer of the queue from a first value to a second value based on an indication that each process operating on a respective entry within the second segment has completed use of the respective entry, and wherein the first value is associated with a beginning of the second segment and the second value is associated with an end of the second segment; and(Col 6, Lines 4-34, (3) the number of storage locations in the current segment is preferably stored in the link entry maintained at the end of the preceding segment and loaded into the register 31 at the commencement of usage of the current segment. The count in register 31 is decremented each time a data-item storage location is written to. Upon the count value in register 31 becoming equal to zero, the producer entity reads the next location (pointed to by the tail pointer) to retrieve the link entry giving the address of the first storage location of the next segment and the size of the segment (in terms of the number of data-item storage locations); these two pieces of information are loaded into the tail-pointer register 30 and the remaining-segment-size register 31 ready for writing the next data item to a new queue segment in a different memory page. Also see Col 7, Lines, 54-63, (16) Col 8, Line 22-33 (20)).
Therefore it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention, to have modified the teachings of Svennebring et al by advancing a tail pointer of the queue from a first value to a second value based on an indication that each process operating on a respective entry within the second segment has completed use of the respective entry, and wherein the first value is associated with a beginning of the second segment and the second value is associated with an end of the second segment; and responsive to advancing the tail pointer, at least one of: providing entries of the second segment to one or more consumer processes of the plurality of processes, or deallocating memory associated with entries of the second segment., as taught by Regache et al (Col 6, Lines 4-34)
One of the ordinary skill in the art would have been motivated to make this modification, by doing so, there are advantages in having the producer entity initiate passing of its P-Index each time the latter is updated as this can be used to indicate to the consumer entity that there is a new data-item to be read, possibly moving the consumer entity from an idle state where it had been residing pending a new data item being available as taught by Regache et al (Col 9, Lines 13-18).
Regarding dependent claim 2, Svennebring et al and Regache et al teach, the method of claim 1.
Svennebring et al further teaches, wherein: the first entry is in a first segment of the plurality of segments (Paragraph [0030] discloses, the first segment is the producer circuitry);
and the second entry is in a second segment of the plurality of segments (Paragraph [0030] discloses, the second segment is the consumer circuitry);
Regarding dependent claim 3, Svennebring et al and Regache et al teach, the method of claim 2.
Regache et al further teaches, wherein the end of the second segment is one of a last entry of the second segment or a beginning entry of a third segment of the plurality of segments (Col 7, Lines, 54-63, (16) discloses, link entry is the end of the segment or beginning of next segment).
Regarding dependent claim 4, Svennebring et al and Regache et al teach, the method of claim 2.
Regache et al further teaches, further comprising determining that a head pointer of the queue and the tail pointer each point to a third segment of the plurality of segments, wherein advancingtail pointe(Col 7, Lines, 54-63, (16) discloses, link entry is the end of the segment or beginning of next segment, which is the tail pointer advances to the next segment where the tail pointer is equal to the head pointer to indicate it is an empty segment or beginning of the new segment).
Regarding dependent claim 5, Svennebring et al and Regache et al teach, the method of claim 2.
Regache et al further teaches, wherein a first section of the one or more sections comprises a tail indicator bit, one or more tail address bits, the first counter, and the second counter (Col 7, Lines, 54-63, (16) discloses, tail bit indicator/ pointing to the address in the queue, tail address bits/ wrap around bit, first counter/ incrementing the enqueue process, second counter/ incrementing the dequeue process. Also see Col 2, Lines 7-18)).
Svennebring et al further teaches, wherein a first section of the one or more sections comprises a tail indicator bit, one or more tail address bits, the first counter, and the second counter (Paragraphs [0062], [0064] discloses, tail bit indicator/ index of the received element, tail address bits/ as last element received in the section, first counter/ incrementing the enqueue process, second counter/ incrementing the dequeue process).
Regarding dependent claim 6, Svennebring et al and Regache et al teach, the method of claim 3.
Regache et al further teaches, wherein the first counter and the second counter each have a guard bit to indicate whethe(Col 7, Lines, 54-63, (16) discloses, first counter and second counter each has link entry to indicate whether each of the process has completed the respective entry).
Svennebring et al further teaches, wherein the first counter and the second counter each have a guard bit to indicate whethe(Paragraph [0047] In some examples, the example enqueue circuitry 210 sets the queue status flag of the received value's source to indicate that circular queue is full based on the total length of the elements are enqueued and dequeued).
Regarding dependent claim 7, Svennebring et al and Regache et al teach, the method of claim 1.,
Svennebring et al further teaches, wherein the first process is a producer process that stores one or more data values in the first entry of the queue (Paragraph [0030] discloses, first process as producer process that stores one or more data values in the queue).
Regarding independent claim 8, Svennebring; Jonas (US 20220043687 A1) teaches a system of managing entries in a queue that comprises a plurality of segments and is shared by a plurality of processes, the system comprising: a memory storing a queue and a data structure associated with the queue (Paragraph [0028], [0059] memory used in a queue), wherein the queue comprises a plurality of segments and the data structure associated with the queue comprises a plurality of sections, and wherein each section of the data structure comprises one or more counters each associated with a segment of the plurality of segments (Paragraph [0076] discloses, plurality of sections, which is total number of elements in a segment and is incremented based on the total number of elements (Examiner interprets sections as elements),
and processing circuitry coupled to the memory, the processing circuitry to: provide a first entry of the queue to a first process of a plurality of processes (Fig. 1, Paragraph [0030] discloses, multi-producer multi-consumer queues (Based on specification [0121] first process can be producer process or consumer process) and;
a second entry of the queue to a second process of the plurality of processes (Fig. 1, Paragraph [0030] discloses, multi-producer multi-consumer queues ( Based on specification [0121] first process can be producer process or consumer process);
responsive to receiving a first signal from the first process (Paragraph [0042] discloses, in response to receiving a signal from the first process/ producer to indicate that the circular queue is not full enqueuing values in the circular queue (Examiner interprets first process as producer circuitry)), modify one or more sections of the data structure associated with the queue(Paragraph [0076] updating the producer index for the new element added in the queue. Also see [0038]), wherein to modify the data structure for the first entry the processing circuitry is to increment a first counter associated with a first segment of the plurality of segments (Paragraph [0076] discloses, plurality of sections, which is total number of elements in a segment and is incremented based on the total number of elements (Examiner interprets sections as elements);
responsive to receiving a second signal from the second process (Paragraph [0049] discloses, in response to receiving a signal from the second process/ consumer to remove/ dequeue the value from the circular queue (Examiner interprets second process as consumer circuitry)), modify the data structure associated with the queue(Paragraph [0064] discloses, modifying the data structure by incrementing/ the values from the second entry to the total length of the elements in a segment by dequeue process);
Svennebring et al fails to explicitly teach, advance a tail pointer of the queue from a first value to a second value based on an indication that each process operating on a respective entry within the second segment has completed use of the respective entry, and wherein the first value is associated with a beginning of the second segment and the second value is associated with an end of the second segment; and responsive to advancing the tail pointer, at least one of: providing entries of the second segment to one or more consumer processes of the plurality of processes, or deallocating memory associated with entries of the second segment.
Regache; Pascal (US 5873089 A) teaches, advancing a tail pointer of the queue from a first value to a second value based on an indication that each process operating on a respective entry within the second segment has completed use of the respective entry, and wherein the first value is associated with a beginning of the second segment and the second value is associated with an end of the second segment; and(Col 6, Lines 4-34, (3) the number of storage locations in the current segment is preferably stored in the link entry maintained at the end of the preceding segment and loaded into the register 31 at the commencement of usage of the current segment. The count in register 31 is decremented each time a data-item storage location is written to. Upon the count value in register 31 becoming equal to zero, the producer entity reads the next location (pointed to by the tail pointer) to retrieve the link entry giving the address of the first storage location of the next segment and the size of the segment (in terms of the number of data-item storage locations); these two pieces of information are loaded into the tail-pointer register 30 and the remaining-segment-size register 31 ready for writing the next data item to a new queue segment in a different memory page. Also see Col 7, Lines, 54-63, (16) Col 8, Line 22-33 (20)).
Therefore it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention, to have modified the teachings of Svennebring et al by advancing a tail pointer of the queue from a first value to a second value based on an indication that each process operating on a respective entry within the second segment has completed use of the respective entry, and wherein the first value is associated with a beginning of the second segment and the second value is associated with an end of the second segment; and responsive to advancing the tail pointer, at least one of: providing entries of the second segment to one or more consumer processes of the plurality of processes, or deallocating memory associated with entries of the second segment., as taught by Regache et al (Col 6, Lines 4-34)
One of the ordinary skill in the art would have been motivated to make this modification, by doing so, there are advantages in having the producer entity initiate passing of its P-Index each time the latter is updated as this can be used to indicate to the consumer entity that there is a new data-item to be read, possibly moving the consumer entity from an idle state where it had been residing pending a new data item being available as taught by Regache et al (Col 9, Lines 13-18).
Regarding dependent claim 9, Svennebring et al and Regache et al teach, the system of claim 8.
Svennebring et al further teaches, wherein: the first entry is in a first segment of the plurality of segments (Paragraph [0030] discloses, the first segment is the producer circuitry);
and the second entry is in a second segment of the plurality of segments (Paragraph [0030] discloses, the second segment is the consumer circuitry).
Regarding dependent claim 10, Svennebring et al and Regache et al teach, teach, the system of claim 9.
Regache et al further teaches, wherein the end of the second segment is one of a last entry of the second segment of a beginning entry of a third segment of the plurality of segments(Col 7, Lines, 54-63, (16) discloses, link entry is the end of the segment or beginning of next segment).
Regarding dependent claim 11, Svennebring et al and Regache et al teach, the system of claim 9.
Regache et al further teaches, wherein the processing circuitry is further to determine that a head pointer of the queue and the tail pointer each point to a third segment of the plurality of segments, wherein to advance the tail pointer, the processing circuitry is to modify the tail pointer to equal a position of the head pointer in response to determining that a number of entries in the third segment between the head pointer and a beginning of a third segment is equal to a counter value of a third counter associated with the third segmen(Col 7, Lines, 54-63, (16) discloses, link entry is the end of the segment or beginning of next segment, which is the tail pointer advances to the next segment where the tail pointer is equal to the head pointer to indicate it is an empty segment or beginning of the new segment).
Regarding dependent claim 12, Svennebring et al and Regache et al teach, the system of claim 9.
Regache et al further teaches, wherein a first section of the one or more sections comprises a tail indicator bit, one or more tail address bits, the first counter, and the second counter (Col 7, Lines, 54-63, (16) discloses, tail bit indicator/ pointing to the address in the queue, tail address bits/ wrap around bit, first counter/ incrementing the enqueue process, second counter/ incrementing the dequeue process. Also see Col 2, Lines 7-18)).
Svennebring et al further teaches, wherein a first section of the plurality of sections comprises a tail indicator bit, one or more tail address bits, the first counter, and the second counter (Paragraphs [0062], [0064] discloses, tail bit indicator/ index of the received element, tail address bits/ as last element received in the section, first counter/ incrementing the enqueue process, second counter/ incrementing the dequeue process).
Regarding dependent claim 13, Svennebring et al and Regache et al teach, the system of claim 10.
Regache et al further teaches, wherein the first counter and the second counter each have a guard bit to indicate whethe (Col 7, Lines, 54-63, (16) discloses, first counter and second counter each has link entry to indicate whether each of the process has completed the respective entry).
Svennebring et al further teaches, wherein the first counter and the second counter each have a guard bit to indicate whethe(Paragraph [0047] In some examples, the example enqueue circuitry 210 sets the queue status flag of the received value's source to indicate that circular queue is full based on the total length of the elements are enqueued and dequeued).
Regarding dependent claim 14, Svennebring et al and Regache et al teach, the system of claim 8.
Svennebring et al further teaches, wherein the first process is a consumer process that performs one or more operations based on data values in the first entry of the queue (Paragraph [0030] discloses, first process as producer process that stores one or more data values in the queue).
Regarding independent claim 15, Svennebring; Jonas (US 20220043687 A1) teaches, a system comprising: a first processor; a second processor; and processing circuitry coupled to the first processor and the second processor (Fig. 17, Paragraph [0144]), the processing circuitry to: provide a first entry of a queue to the first processor (Fig. 1, Paragraph [0030] discloses, multi-producer multi-consumer queues (Based on specification [0121] first process can be producer process or consumer process), wherein the queue comprises a plurality of segments (Paragraph [0030] the queue may be divided into a plurality of segments);
provide a second entry of the queue to the second processor (Fig. 1, Paragraph [0030] discloses, multi-producer multi-consumer queues ( Based on specification [0121] first process can be producer process or consumer process);
responsive to receiving a first signal from the first processor (Paragraph [0042] discloses, in response to receiving a signal from the first process/ producer to indicate that the circular queue is not full enqueuing values in the circular queue (Examiner interprets first process as producer circuitry)), modify one or more sections of a data structure associated with the queue (Paragraph [0076] updating the producer index for the new element added in the queue. Also see [0038]), wherein each section of the data structure comprises one or more counters each associated with a segment of the plurality of segments, and wherein to modify the data structure associated with the queue for the first entry, the processing circuitry is to increment a first counter associated with a first segment of the plurality of segments (Paragraph [0076] discloses, plurality of sections, which is total number of elements in a segment and is incremented based on the total number of elements (Examiner interprets sections as elements);
responsive to receiving a second signal from the second processor (Paragraph [0049] discloses, in response to receiving a signal from the second process/ consumer to remove/ dequeue the value from the circular queue (Examiner interprets second process as consumer circuitry)), modify the data structure associated with the queue(Paragraph [0064] discloses, modifying the data structure by incrementing/ the values from the second entry to the total length of the elements in a segment by dequeue process);
Svennebring et al fails to explicitly teach, advance a tail pointer of the queue from a first value to a second value based on an indication that each processor operating on a respective entry within the second segment has completed use of the respective entry, and wherein the first value is associated with a beginning of the second segment and the second value is associated with an end of the second segment; and responsive to advancing the tail pointer, at least one of: providing entries of the second segment to one or more consumer processes, or deallocating memory associated with entries of the second segment.
Regache; Pascal (US 5873089 A) teaches, advance a tail pointer of the queue from a first value to a second value based on an indication that each process operating on a respective entry within the second segment has completed use of the respective entry, and wherein the first value is associated with a beginning of the second segment and the second value is associated with an end of the second segment; and(Col 6, Lines 4-34, (3) the number of storage locations in the current segment is preferably stored in the link entry maintained at the end of the preceding segment and loaded into the register 31 at the commencement of usage of the current segment. The count in register 31 is decremented each time a data-item storage location is written to. Upon the count value in register 31 becoming equal to zero, the producer entity reads the next location (pointed to by the tail pointer) to retrieve the link entry giving the address of the first storage location of the next segment and the size of the segment (in terms of the number of data-item storage locations); these two pieces of information are loaded into the tail-pointer register 30 and the remaining-segment-size register 31 ready for writing the next data item to a new queue segment in a different memory page. Also see Col 7, Lines, 54-63, (16) Col 8, Line 22-33 (20)).
Therefore it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention, to have modified the teachings of Svennebring et al by advancing a tail pointer of the queue from a first value to a second value based on an indication that each process operating on a respective entry within the second segment has completed use of the respective entry, and wherein the first value is associated with a beginning of the second segment and the second value is associated with an end of the second segment; and responsive to advancing the tail pointer, at least one of: providing entries of the second segment to one or more consumer processes of the plurality of processes, or deallocating memory associated with entries of the second segment., as taught by Regache et al (Col 6, Lines 4-34)
One of the ordinary skill in the art would have been motivated to make this modification, by doing so, there are advantages in having the producer entity initiate passing of its P-Index each time the latter is updated as this can be used to indicate to the consumer entity that there is a new data-item to be read, possibly moving the consumer entity from an idle state where it had been residing pending a new data item being available as taught by Regache et al (Col 9, Lines 13-18).
Regarding dependent claim 16, Svennebring et al and Regache et al teach, the system of claim 15.
Svennebring et al further teaches, wherein: the first entry is in a first segment of the plurality of segments (Paragraph [0030] discloses, the first segment is the producer circuitry);
and the second entry is in a second segment of the plurality of segments (Paragraph [0030] discloses, the second segment is the consumer circuitry);
Regarding dependent claim 17, Svennebring et al and Regache et al teach, the system of claim 16.
Regache et al further teaches, wherein the end of the second segment is one of a last entry of the second segment or a beginning entry of a third segment of the plurality of segments (Col 7, Lines, 54-63, (16) discloses, link entry is the end of the segment or beginning of next segment).
Regarding dependent claim 18, Svennebring et al and Regache et al teach, the system of claim 16.
Regache et al further teaches, wherein the processing circuitry is further to determine that a head pointer of the queue and the tail pointer each point to a third segment of the plurality of segments, wherein to advance the tail pointer, the processing circuitry is to modify the tail pointer to equal a position of the head pointer in response to determining that a number of entries in the third segment between the head pointer and a beginning of the third segment is equal to a counter value of a third counter associated with the third segmen(Col 7, Lines, 54-63, (16) discloses, link entry is the end of the segment or beginning of next segment, which is the tail pointer advances to the next segment where the tail pointer is equal to the head pointer to indicate it is an empty segment or beginning of the new segment).
Regarding dependent claim 19, Svennebring et al and Regache et al teach, the system of claim 16.
Regache et al further teaches, wherein a first section of the one or more sections comprises a tail indicator bit, one or more tail address bits, the first counter, and the second counter (Col 7, Lines, 54-63, (16) discloses, tail bit indicator/ pointing to the address in the queue, tail address bits/ wrap around bit, first counter/ incrementing the enqueue process, second counter/ incrementing the dequeue process. Also see Col 2, Lines 7-18)).
Svennebring et al further teaches, wherein a first section of the one or more sections comprises a tail indicator bit, one or more tail address bits, the first counter, and the second counter (Paragraphs [0062], [0064] discloses, tail bit indicator/ index of the received element, tail address bits/ as last element received in the section, first counter/ incrementing the enqueue process, second counter/ incrementing the dequeue process).
Regarding dependent claim 20, Svennebring et al and Regache et al teach the system of claim 17.
Regache et al further teaches, wherein the first counter and the second counter each have a guard bit to indicate whether each process operating on a respective entry within the second segment has completed use of the respective entry (Col 7, Lines, 54-63, (16) discloses, first counter and second counter each has link entry to indicate whether each of the process has completed the respective entry).
Svennebring et al further teaches, wherein the first counter and the second counter each have a guard bit to indicate whether each process operating on a respective entry within the second segment has completed use of the respective entry (Paragraph [0047] In some examples, the example enqueue circuitry 210 sets the queue status flag of the received value's source to indicate that circular queue is full based on the total length of the elements are enqueued and dequeued).
Closest Prior Art
10. The prior art made of record and not relied upon is considered pertinent to the applicant’s disclosure.
Regache; Pascal (US 5873089 A) teaches, A data handling system is provided in which a circular queue formed in paged memory is used to buffer the transfer of data items between a producer entity and a consumer entity. The producer entity maintains a tail pointer into the queue to indicate the storage location next to be written to; similarly, the consumer entity maintains a head pointer to indicate the storage location next to be read. Since the head and tail pointers may point to different memory pages and these may not have been assigned in a contiguous block to the circular queue, the derivation of queue status information using the head and tail pointers is complex. To simplify this task, the producer and consumer entities maintain producer and consumer indexes for the next write and read positions based on a logical view of the queue as a circular continuum of storage locations.
11. Examiner has pointed out particular references contained in the prior arts of record in the body of this action for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and Figures may apply as well. It is respectfully requested from the applicant, in preparing the response, to consider fully the entire references as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior arts or disclosed by the examiner. It is noted that any citation to specific pages, columns, figures, or lines in the prior art references any interpretation of the references should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. In re Heck, 699 F.2d 1331-33, 216 USPQ 1038-39 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968))).
Conclusion
Applicant’s amendments/Arguments necessitated new grounds of rejection as presented in this office action. THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUMAN RAJAPUTRA whose telephone number is (571) 272-4669. The examiner can normally be reached between 8:00 AM - 5:00 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tony Mahmoudi (571) 272-4078 can be reached. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S. R./
Examiner, Art Unit 2163
/TONY MAHMOUDI/Supervisory Patent Examiner, Art Unit 2163
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