Prosecution Insights
Last updated: April 19, 2026
Application No. 19/185,687

DISPLAY DEVICE, DISPLAY SYSTEM, AND ELECTRONIC DEVICE

Non-Final OA §102§103
Filed
Apr 22, 2025
Examiner
WILSON, DOUGLAS M
Art Unit
2622
Tech Center
2600 — Communications
Assignee
Samsung Display Co., Ltd.
OA Round
1 (Non-Final)
75%
Grant Probability
Favorable
1-2
OA Rounds
2y 9m
To Grant
91%
With Interview

Examiner Intelligence

Grants 75% — above average
75%
Career Allow Rate
320 granted / 427 resolved
+12.9% vs TC avg
Strong +16% interview lift
Without
With
+16.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
25 currently pending
Career history
452
Total Applications
across all art units

Statute-Specific Performance

§101
1.9%
-38.1% vs TC avg
§103
56.5%
+16.5% vs TC avg
§102
22.5%
-17.5% vs TC avg
§112
14.4%
-25.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 427 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1-20 are pending. Priority Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Korea on 17 June 2024 and an application filed in Korea on 18 October 2024. It is noted, however, that applicant has not filed a certified copy of the 10-2024-0078154 application as required by 37 CFR 1.55. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-6, and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin (US 2021/0295755). Regarding Claim 1 (Original), Lin teaches a display device comprising: a display panel [fig. 5 @500] comprising sub-pixels [¶0023, “the display area 111 includes multiple data lines DL and multiple gate lines GL1-GL3. The data lines DL and the gate lines GL1- GL3 are respectively connected to multiple display pixels (not shown) arranged in a matrix manner in the display area 111”] electrically connected to gate lines [fig. 5 @GL], data lines [fig. 5 @DL], and auxiliary data lines [fig. 5 @AD]; a gate driver [fig. 5 @520] on a side of the display panel [fig. 5 illustrates], and configured to output gate signals to the gate lines [¶0047, “the display area 111 includes multiple gate lines GL connected to the gate driving circuit 520”]; and a data driver [fig. 5 @5301] configured to output data signals to the data lines [fig. 5 @DL] through [fig. 5 illustrates 5301 connected to DL through AD] the auxiliary data lines [fig. 5 @AD]. Regarding Claim 2 (Original), Lin teaches the display device according to Claim 1, wherein the data driver [fig. 5 @5301] is on the side of the display panel on which the gate driver [fig. 5 @530] is located, or is on another side of the display panel that is opposite to the one side [alternate limitation not addressed]. Regarding Claim 3 (Original), Lin teaches the display device according to Claim 1, wherein the display panel [fig. 5 @500] has a long side [fig. 5 @E1] extending in a first direction [fig. 5 @horizontal], and a short side [fig. 5 @ SE1] extending in a second direction [fig. 5 @horizontal] crossing the first direction, and wherein the data driver [fig. 5 @ 5301] is on the short side. Regarding Claim 4 (Original), Lin teaches the display device according to Claim 3, wherein the gate lines [fig. 5 @GL] and the auxiliary data lines [fig. 5 @AD] extend in the first direction [fig. 5 @horizontal], and wherein the data lines [fig. 5 @DL] extend in the second direction [fig. 5 @vertical]. Regarding Claim 5 (Original), Lin teaches the display device according to Claim 4, wherein the data lines are respectively electrically connected to at least one of the auxiliary data lines [fig. 5 illustrates claimed structure]. Regarding Claim 6 (Original), Lin teaches the display device according to Claim 4, wherein the data lines comprise: a first data line electrically connected to a first column of the sub-pixels; a second data line electrically connected to a second column of the sub-pixels; and a third data line electrically connected to a third column of the sub-pixels [¶0023 teaches all the pixels are formed into a matrix of rows and columns where the data lines extending vertically supply data voltages to all the pixels, teaching is equivalent to a data line corresponds to a pixel column], and wherein the auxiliary data lines comprise: a first auxiliary data line electrically connected to the first data line; a second auxiliary data line electrically connected to the second data line; and a third auxiliary data line electrically connected to the third data line [fig. 5 teaches a single auxiliary data line providing data signals to an associated data line]. Regarding Claim 8 (Original), Lin teaches the display device according to Claim 4, wherein a number of the data lines [fig. 5 illustrates 6] corresponds to a number of columns of the sub-pixels [¶0023, “the display area 111 includes multiple data lines DL … The data lines DL … connected to multiple display pixels (not shown) arranged in a matrix manner in the display area 111. The data driving circuit 130 is configured to generate data voltage to the data lines DL, and the data driving circuit 130 provides the data voltage to each of display pixels of the display area 111 through the data lines DL”], and wherein a number of the auxiliary data lines [fig. 5 illustrates 6 aux data lines AD] is a positive integer multiple [x1] of the number of the columns [one auxiliary data line provides data voltages to the specific connected data line which supplies data voltages to attached column of pixels as taught by ¶0023]. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Wu (US 2022/0344428). All reference is to Lin unless otherwise indicated. Regarding Claim 9 (Original), Lin teaches the display device according to Claim 8 Lin does not teach the display panel comprises a silicon substrate Wu teaches a display panel comprises a silicon substrate [¶0096, “In some embodiments, the display panel uses a silicon substrate as a base substrate 101. The pixel circuit, the data driving circuit 14 and the scan driving circuit 13 may all be integrated on the silicon substrate. In this case, since the silicon-based circuit may achieve higher accuracy, the data driving circuit 14 and the scan driving circuit 13 may also be formed in the region corresponding to the display region of the display panel, and are not necessarily located in the non-display region”] Before the application was filed it would have been obvious to one of ordinary skill in the art to incorporate the concept of providing silicon substrate in a display device, as taught by Wu, into the display device taught by Lin, in order to facilitate the formation of the display data and scan driving circuits in the display region of the display device (Wu: ¶0096). Regarding Claim 10 (Original), Lin in view of Wu teaches the display device according to Claim 9, wherein the display device is configured to provide virtual reality (VR) or augmented reality (AR) [Wu: ¶0061, “Micro OLEDs are widely used in AR and VR fields. With the continuous development of technology, higher resolution is required. Therefore, higher requirements are put forward on the structural design of the display panel, such as the arrangement of the pixels and the signal lines”, ¶0062, “In the display panel provided by at least one embodiment of the disclosure, optimized layout and wiring is applied in designing, such that an area of sub-pixel being 5.45 μm×13.6 μm may be achieved, achieving a high resolution (PPI, Pixels Per Inch), an optimized arrangement of the pixel circuit array, and a better display effect”]. Claims 7, 11-13, and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Jin (US 10,950,679). All reference is to Lin unless otherwise indicated. Regarding Claim 7 (Original), Lin teaches the display device according to Claim 4, wherein the data lines comprise a first data line [fig. 5 @DL11] electrically connected to a first column of the sub-pixels [construed as rightmost column in area B1], and wherein one or more of the auxiliary data lines [fig. 5 @AD11] are electrically connected to the first data line [fig. 5 @DL11] Lin does not teach auxiliary data lines connected to data lines through first contact holes Jin teaches auxiliary data lines connected to data lines through first contact holes [vias and contact holes are equivalent connections, col 3 lines 47-52, “Vertical portions DV and horizontal portions DH may be formed in different patterned metal layers in display 14 and may be connected using respective vias 40 (e.g., metal vias that extend between the metal layer containing vertical portions DV and the metal layer containing horizontal portions DH)] Before the application was filed it would have been obvious to one of ordinary skill in the art to connect wiring lines in different conductive layers using contact holes, as taught by Jin, into the display device taught by Lin in order to electrically connect wiring lines routed in different conductive layers of a display stackup without affecting adjacent wiring lines. Regarding Claim 11 (Original), Lin teaches a display device comprising: a display panel [fig. 5 @500] having a long side [fig. 5 @E1] extending in a first direction [fig. 5 @horizontal], and a short side [fig. 5 @SE1] extending in a second direction [fig. 5 @vertical] crossing the first direction [fig. 5 @horizontal], and comprising sub-pixels [¶0023] electrically connected to gate lines [fig. 5 @GL], auxiliary data lines extending in the first direction [fig. 5 @AD extending horizontally], and data lines extending in the second direction [fig. 5 DL extending vertically], and electrically connected to the auxiliary data lines [¶0049 teaches DL lines connected to AD lines]; a gate driver [fig. 5 @520] on the short side of the display panel [fig. 5 @SE1], and electrically connected to the gate lines [fig. 5 @GL, ¶0047, “the display area 111 includes multiple gate lines GL connected to the gate driving circuit 520]; and a data driver [fig. 5 @5301] on the short side of the display panel or on a side of the display panel [fig. 5 @5302] that is opposite to the short side [fig. 5 @SE2], and electrically connected [¶0048, “the auxiliary data lines AD21˜AD23 are configured to connect the data lines DL21˜DL23 to the data driving circuit 5301”] to the data lines [fig. 5 @DL] Lin does not teach the data lines are electrically connected to the auxiliary data lines through contact holes Jin teaches data lines [fig. 2 @DV] are electrically connected to auxiliary data lines [fig. 2 @DH] through contact holes [vias and contact holes are equivalent connections, col 3 lines 47-52, “Vertical portions DV and horizontal portions DH may be formed in different patterned metal layers in display 14 and may be connected using respective vias 40 (e.g., metal vias that extend between the metal layer containing vertical portions DV and the metal layer containing horizontal portions DH)] Before the application was filed it would have been obvious to one of ordinary skill in the art to connect wiring lines in different conductive layers using contact holes, as taught by Jin, into the display device taught by Lin in order to electrically connect wiring lines routed in different conductive layers of a display stackup without affecting adjacent wiring lines. Regarding Claim 12 (Original), Lin in view of Jin teaches the display device according to Claim 11, wherein the data lines comprise a first data line [fig. 5 @DL11] electrically connected to a first column of the sub-pixels [construed as rightmost column in area B1], and wherein one or more of the auxiliary data lines [fig. 5 @AD11] are electrically connected to the first data line [fig. 5 @DL11] through first contact holes [Jin: col 3 lines 47-52 teaches connecting data and auxiliary data lines through contact holes]. Regarding Claim 13 (Original), Lin in view of Jin teaches the display device according to Claim 12, wherein a number of the data lines [fig. 5 illustrates 6] corresponds to a number of columns of the sub-pixels [¶0023, “the display area 111 includes multiple data lines DL … The data lines DL … connected to multiple display pixels (not shown) arranged in a matrix manner in the display area 111. The data driving circuit 130 is configured to generate data voltage to the data lines DL, and the data driving circuit 130 provides the data voltage to each of display pixels of the display area 111 through the data lines DL”], and wherein a number of the auxiliary data lines [fig. 5 illustrates 6 aux data lines AD] is a positive integer multiple [x1] of the number of the columns [one auxiliary data line provides data voltages to the specific connected data line which supplies data voltages to attached column of pixels as taught by ¶0023]. Regarding Claim 16 (Original), Lin teaches an electronic device comprising a display system comprising: a display device [fig. 5 @500] comprising: a display panel [fig. 5 @500] comprising sub-pixels [¶0023, “the display area 111 includes multiple data lines DL and multiple gate lines GL1-GL3. The data lines DL and the gate lines GL1- GL3 are respectively connected to multiple display pixels (not shown) arranged in a matrix manner in the display area 111”] electrically connected to gate lines [fig. 5 @GL], data lines [fig. 5 @DL], and auxiliary data lines [fig. 5 @AD]; a gate driver [fig. 5 @520] on a side of the display panel [fig. 5 illustrates], and configured to output gate signals to the gate lines [¶0047, “the display area 111 includes multiple gate lines GL connected to the gate driving circuit 520”]; and a data driver [fig. 5 @5301] configured to output data signals to the data lines [fig. 5 @DL] through [fig. 5 illustrates 5301 connected to DL through AD] the auxiliary data lines [fig. 5 @AD] Lin does not teach a display processor Jin teaches a display processor [col 2 lines 24-29, “As shown in FIG. 1, electronic device 10 may have control circuitry 16. Control circuitry 16 may include storage and processing circuitry for supporting the operation of device 10 … The processing circuitry may be based on one or more microprocessors”] Before the application was filed it would have been obvious to one of ordinary skill in the art to incorporate the concept of providing a processor in a display device, as taught by Jin, into the display device taught by Lin, in order to support operation of the display device. Regarding Claim 17 (Original), Lin in view of Jin teaches the electronic device according to Claim 16, wherein the data driver [fig. 5 @5301] is on the side of the display panel on which the gate driver [fig. 5 @520] is located, or is on another side of the display panel that is opposite to the one side [alternate limitation not addressed]. Regarding Claim 18 (Original), Lin in view of Jin teaches the electronic device according to Claim 16, wherein the display panel [fig. 5 @500] has a long side [fig. 5 @E1] extending in a first direction [fig. 5 @horizontal], and a short side [fig. 5 @ SE1] extending in a second direction [fig. 5 @horizontal] crossing the first direction, and wherein the data driver [fig. 5 @ 5301] is on the short side. Regarding Claim 19 (Original), Lin in view of Jin teaches the electronic device according to Claim 18, wherein the gate lines [fig. 5 @GL] and the auxiliary data lines [fig. 5 @AD] extend in the first direction [fig. 5 @horizontal], and wherein the data lines [fig. 5 @DL] extend in the second direction [fig. 5 @vertical]. Regarding Claim 20 (Original), Lin in view of Jin teaches the electronic device according to Claim 19, wherein the data lines [fig. 5 @DL] are respectively electrically connected to at least one [fig. 5 illustrates claimed structure] of the auxiliary data lines [fig. 5 @AD]. Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Jin and Wu (US 2022/0344428). All reference is to Lin unless otherwise indicated. Regarding Claim 14 (Original), Lin in view of Jin teaches the display device according to claim 13 Lin in view of Jin does not teach the display panel comprises a silicon substrate Wu teaches a display panel comprises a silicon substrate [¶0096, “In some embodiments, the display panel uses a silicon substrate as a base substrate 101. The pixel circuit, the data driving circuit 14 and the scan driving circuit 13 may all be integrated on the silicon substrate. In this case, since the silicon-based circuit may achieve higher accuracy, the data driving circuit 14 and the scan driving circuit 13 may also be formed in the region corresponding to the display region of the display panel, and are not necessarily located in the non-display region”] Before the application was filed it would have been obvious to one of ordinary skill in the art to incorporate the concept of providing silicon substrate in a display device, as taught by Wu, into the display device taught by Lin in view of Jin, in order to facilitate the formation of the display data and scan driving circuits in the display region of the display device (Wu: ¶0096). Regarding Claim 15 (Original), Lin in view of Jin and Wu teaches the display device according to Claim 14, wherein the display device is configured to provide virtual reality (VR) or augmented reality (AR) [Wu: ¶0061, “Micro OLEDs are widely used in AR and VR fields. With the continuous development of technology, higher resolution is required. Therefore, higher requirements are put forward on the structural design of the display panel, such as the arrangement of the pixels and the signal lines”, ¶0062, “In the display panel provided by at least one embodiment of the disclosure, optimized layout and wiring is applied in designing, such that an area of sub-pixel being 5.45 μm×13.6 μm may be achieved, achieving a high resolution (PPI, Pixels Per Inch), an optimized arrangement of the pixel circuit array, and a better display effect”]. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Douglas Wilson whose telephone number is (571)272-5640. The examiner can normally be reached 1000-1700 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Patrick Edouard can be reached at 571-272-7603. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Douglas Wilson/Primary Examiner, Art Unit 2622
Read full office action

Prosecution Timeline

Apr 22, 2025
Application Filed
Jan 07, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
75%
Grant Probability
91%
With Interview (+16.1%)
2y 9m
Median Time to Grant
Low
PTA Risk
Based on 427 resolved cases by this examiner. Grant probability derived from career allow rate.

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