DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 7, and 9 are rejected under 35 U.S.C. §102(a)(1) as being anticipated by Agarwal et al. (“Agarwal”) – US 2015/0371956, cited in the IDS filed April 22, 2025.
Regarding claim 1, Agarwal discloses a semiconductor structure (Figs. 3A-3B), comprising:
a substrate (302; Figs. 3A-B; ¶ 0040 “silicon wafer 302”);
a functional circuit structure (350, Figs. 3A-B; ¶ 0040 “least one die 350”) disposed in an area of the substrate (Figs. 3A-3B); and
a first three-dimensional structure (302, 312, 312a, 312b; Figs. 3A-B see the first annotated Fig. 3B infra; ¶ 0040) comprising at least one continuous trench (312, 312a, 312b; Figs. 3A-B; ¶ 0003, 0028-0029, 0040 “Wafer 302 has two wafer CSTs 312a and 312b”) that forms an uninterrupted empty space within the substrate (Fig. 3A; ¶ 0028 “A wafer level crackstop (“wafer CST”) includes one or more trenches formed as rings around the periphery of the wafer near the wafer edge.”) and that extends into the substrate from a top surface of the substrate (Fig. 3B the top surface of 302) towards an upper surface of the bottom portion of the substrate (Figs. 3A-B; ¶ 0040 “FIG. 3B is a cross section of the semiconductor structure shown in FIG. 3A along line A-A′.”) and that surrounds the area of the substrate containing the functional circuit structure (Figs. 3A-B trenches 312, 312a, 312b surround the area of the substrate 302 containing dies 350; ¶ 0003, 0028, 0040),
wherein the functional circuit structure comprises a second three-dimensional structure (302, 350, 352, 354; Figs. 3A-B see the second annotated Fig. 3B infra; ¶ 0040), and
wherein the first three-dimensional structure and the second three-dimensional structure each comprises a protruding structure (Fig. 3B; the protruding structure of the first three-dimensional structure is located between the substrate 302 on the outside of 312a and the substrate 302 on the inside of 312b – see the first annotated Fig. 3B infra; the protruding structure of the second three-dimensional structure is located between the substrate 302 on the left side of the leftmost 354 and the substrate 302 on the right side of the rightmost 354 – see the second annotated Fig. 3B infra; thus the two protruding structures are between the two outside arrows marked on the first and second annotated Fig. 3B infra), the protruding structure extending upwards from the upper surface of the bottom portion of the substrate (Fig. 3B; ¶ 0040) and having a pattern comprising a plurality of discontinuous walls (the protruding structure of the first three-dimensional structure and the protruding structure of the second three-dimensional structure have “discontinuous walls” because the walls/surfaces are uneven and different sizes), and
wherein the first three-dimensional structure and the second three-dimensional structure have a same three-dimensional pattern (312a, 312b, and 354 are continuous trenches; Figs. 3A-B; ¶ 0003, 0028, 0040), but the first three-dimensional structure has at least one larger three-dimensional pattern critical dimension (length) than the second three-dimensional structure (Figs. 3A-B; ¶ 0040).
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Regarding claim 2, Agarwal discloses the semiconductor structure of claim 1, wherein the substrate is a wafer (0003, 0040) having a useable die area (the area inside the innermost edge of 312b; Fig. 3A) and an exclusion area (the area marked by the “X” in Fig. 3A, paragraph 0040), and wherein the area of the substrate containing the functional circuit structure corresponds to the useable die area of the wafer (Fig. 3A).
Regarding claim 3, Agarwal discloses the semiconductor structure of claim 2, wherein the at least one continuous trench of the first three-dimensional structure includes a continuous trench (312a, 312b) which is located in the exclusion area of the wafer (Fig. 3A; ¶ 0040 “Wafer 302 has two wafer CSTs 312a and 312b on the inside of wafer edge 301.” and “This defines the periphery of the wafer 302.”).
Regarding claim 4, Agarwal discloses the semiconductor structure of claim 1, wherein the area of the substrate containing the functional circuit structure comprises a matrix of unit chip areas (the functional circuits 350 inside the innermost edge of 312b; Fig. 3A), each unit chip area surrounded by a respective scribe region (the respective scribe region is the continuous area immediately outside of functional circuit 350 that includes trench 354), wherein the functional circuit structure is disposed in a unit chip area of the unit chip areas (350 is located inside the innermost edge of 312b; Fig. 3A), and wherein the at least one continuous trench of the first three-dimensional structure includes a second continuous trench (in this instance “a second continuous trench” 354; Figs. 3A-3B; ¶ 0028, 0040 “Each die 350 has…at least one die CST 354 formed in the bulk silicon wafer 302.”) which is located in the respective scribe region of the unit chip area (Figs. 3A-3B; ¶ 0028, 0040).
Regarding claim 7, Agarwal discloses the semiconductor structure of claim 1, comprising a layer stack disposed conformally over the protruding structure of the first three-dimensional structure or the second three-dimensional structure (0040 “filling the die CSTs with the same material(s)”).
Regarding claim 9, Agarwal discloses the semiconductor structure of claim 1, wherein the at least one larger three- dimensional pattern critical dimension comprises a width (the distance between the innermost edge of innermost CST 312b and the outermost edge of outermost CST 312a) separating adjacent elements (adjacent CST’s 312a, 312b; Figs. 3A-B; 0040) of the (same) three-dimensional pattern.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. §103 as being unpatentable over Agarwal et al. (“Agarwal”), US 2015/0371956 as applied to Claim 1 above, and further in view of Zechmann et al. (“Zechmann”), US 2018/0247869, cited in the IDS filed April 22, 2025.
Regarding Claim 5, Agarwal discloses a second continuous trench (354), a unit chip area (350) and a scribe region (the respective scribe region is the continuous area immediately outside of functional circuit 350 that includes trench 354).
Agarwal lacks specifically wherein the second continuous trench of the first three-dimensional structure is located between the unit chip area and a designated dicing lane region of the respective scribe region (note specifically the designated dicing lane region in the particular location as claimed is missing in Agarwal).
Zechmann discloses “dicing region between two crack stopping trenches to singulate the wafer into individual semiconductor chips” (¶ 0026).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to modify Agarwal to include the dicing region between two crack stopping trenches, as taught by Zechmann, in order to perform “a simple, low-cost mechanical sawing process” (¶ 0026 of Zechmann).
Claims 6 and 8 are rejected under 35 U.S.C. §103 as being unpatentable over Agarwal et al. (“Agarwal”), US 2015/0371956 as applied to Claim 1 above, and further in view of Wang et al. (“Wang”), US 2020/0006224, cited in the IDS filed April 22, 2025.
Regarding Claim 6, Agarwal discloses a protruding structure (350).
Agarwal does not disclose wherein all corners of the protruding structure are rounded.
Wang discloses wherein all corners of the protruding structure are rounded (Fig. 2; ¶ 0023 states that “the trench 40 and the via opening 42 are illustrated as being substantially vertical with rounding at corners”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to modify Agarwal to include rounded corners of a protruding structure, as taught by Wang, in order to facilitate subsequent “conformal deposition” of layers (¶ 0027: Fig. 3; A conformal deposition of layers ensures that the entire surface of the layers contacts the corner of the protruding structure. Also, ¶ 0063 states a “conformal deposition can decrease an amount of time to fill a trench, which can increase throughput during processing and decrease costs”. It is noted that ¶0014 of Wang says the device can be a capacitor (which is the device in the present application)).
Regarding claim 8, Agarwal discloses the protruding structure of claim 7.
Agarwal does not disclose wherein a corner of the protruding structure is rounded. In addition, Agarwal does not disclose a curvature radius of the rounded corner is greater than a double of a thickness of an insulator layer of the layer stack.
Wang discloses wherein a corner of the protruding structure is rounded (Fig. 2; ¶ 0023 states that “the trench 40 and the via opening 42 are illustrated as being substantially vertical with rounding at corners”), and wherein a curvature radius of the rounded corner is greater than a double of a thickness of an insulator layer of the layer stack (Wang states in ¶ 0026 that “Dimensions, ratios, and angles can vary based on technology generation nodes in which various aspects are implemented and/or based on various processes used. Therefore, Wang teaches that in certain instances it may be optimal for a curvature radius of the rounded corner to be greater than the double of a thickness of an insulator layer).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to modify Agarwal to include rounded corners of a protruding structure, as taught by Wang, including having a curvature radius of the rounded corner greater than a double of a thickness of an insulator layer in order to facilitate subsequent “conformal deposition” of layers for technology generation (¶ 0026 and 0027: Fig. 3; A conformal deposition of layers ensures that the entire surface of the layers contacts the corner of the protruding structure. Also, ¶ 0063 states a “conformal deposition can decrease an amount of time to fill a trench, which can increase throughput during processing and decrease costs”. It is noted that ¶0014 of Wang says the device can be a capacitor (which is the device in the present application)) of the layer stack.
Claim 10 is rejected under 35 U.S.C. §103 as being unpatentable over Agarwal et al. (“Agarwal”), US 2015/0371956 as applied to Claim 1 above, and further in view of Chu et al. (“Chu”), US 2015/0340346, cited in the IDS filed April 22, 2025.
Regarding Claim 10, Agarwal discloses a layer stack disposed conformally over the protruding structure of the first three-dimensional structure and the second three-dimensional structure (0040 “filling the die CSTs with the same material(s)”), said layer stack filling the second three-dimensional structure (0040 “filling the die CSTs with the same material(s)”).
Agarwal does not disclose but leaving an empty space in the first three-dimensional structure.
Chu discloses but leaving an empty space in the first three-dimensional structure (element 40; Fig. 9; ¶ 0056 “In the street region, the polymer 30 is only a covering layer and an Air gap 40 could be formed.”.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to modify Agarwal to include an air gap, as taught by Chu, because the air gap 40 reduces the amount of insulation in region 40 to reduce the overall cost of the semiconductor structure. (In addition, air gaps are a preferred insulator because air has a low dielectric constant close to 1.0. Furthermore, air gaps allow the structure to be “more flexible” ¶0062).
Conclusion
Prior art made of record and not relied upon is considered pertinent to the applicant’s disclosure. Baek et al., US 2019/0237414, discloses a semiconductor structure having a substrate, a functional circuit structure disposed in an area of the substrate, and a first three-dimensional structure comprising at least one continuous trench. Macelwee et al, US 10,283,501, discloses a semiconductor structure having a substrate, a functional circuit structure disposed in an area of the substrate, and a first three-dimensional structure comprising at least one continuous trench. Chiein et al., US,535,694, discloses a semiconductor structure having a substrate, a functional circuit structure disposed in an area of the substrate, and a first three-dimensional structure comprising at least one continuous trench.
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/R.K./Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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