DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 5 is objected to because of the following informalities: in line 4, replace “pair of transistors MOS” with --pair of MOS transistors--. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 1, in line 3, respectively, it is unclear what is meant by the phrase “by means of a first path at least inductive”. Similarly, in line 4, it is unclear what is meant by the phrase “by means of a second path at least inductive”. The examiner will presume for examination purposes that the first and second paths each have an inductance.
Claims 11 and 13 contain a similar issue (see lines 2-5 and 2-4, respectively) and therefore are rejected for the same reason.
All claims that are not specifically addressed are rejected due to a dependency.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 13, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Chevalier (U.S. Patent Application Publication Number 2012/0235654) and Childs et al. (U.S. Patent Application Publication Number 2015/0303800).
Regarding Claim 1, Chevalier discloses a voltage limiting circuit (Figure 5, item Cl’) comprising:
a first terminal (Figure 5, item Cl’; i.e., upper terminal) capable of receiving a first supply voltage from a first initial voltage (i.e., VDD) by means of a first path at least inductive (Figure 5, item CN1, paragraph 0044),
a second terminal (Figure 5, item Cl’; i.e., lower terminal) capable of receiving a second supply voltage from a second initial voltage (i.e., ground) by means of a second path at least inductive (Figure 5, item CN2, paragraph 0044), wherein a voltage difference between the first terminal and the second terminal being an overvoltage (Figure 4, paragraph 0013),
a first MOS transistor having a drain and a source respectively connected to the first terminal and the second terminal (Figure 5, item P1, paragraph 0044).
Chevalier does not expressly disclose a control means, triggerable by the overvoltage and configured to automatically switch the first MOS transistor to a conducting state when the overvoltage reaches a first value and to limit the overvoltage to a second value higher than the first value.
In the same field of endeavor (e.g., overvoltage limiting techniques), Childs teaches a control means, triggerable by the overvoltage and configured to automatically switch the first MOS transistor to a conducting state when the overvoltage reaches a first value and to limit the overvoltage to a second value higher than the first value (Figure 6b, paragraphs 0040-0041; i.e., the “first value” being Vlower and the “second value” being Vupper).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Childs’ teachings of overvoltage limiting techniques with the teachings of Chevalier, for the purpose of ensuring protection against overvoltages while reducing the risk of instability or inadvertent triggering.
Regarding Claim 2, Chevalier discloses wherein the control means include: a first resistor (Figure 5, item R1) connected between a gate of the first transistor and the second terminal, a capacitive divider (Figure 5, items C1 and CL) connected between the first transistor and the first terminal, and including a coupling capacitor (Figure 5, item C1) connected between the first terminal and the gate of the first transistor as well as a gate/source capacitor of the first transistor, and a resistor (Figure 5, item R1) of the first transistor in its conducting state.
Regarding Claim 3, Chevalier discloses wherein the resistor of the first transistor in its conducting state has a value chosen to limit to a limit value the value of a current passing through the first transistor in its conducting state (paragraph 0044).
Regarding Claim 4, Chevalier discloses a second MOS transistor (Figure 5, item P2) cascoded with the first MOS transistor and connected to the first terminal, a second resistor (Figure 5, item R1) connected between the gate of a second transistor (Figure 5, item P3) and the first terminal, and a second capacitor (Figure 5, item C1) connected between the gate of the second transistor and the first terminal.
Regarding Claim 5, Chevalier discloses a switched-mode power supply device (paragraph 0006) comprising:
an assembly (Figure 5) including the voltage limiting circuit of claim 1 having its first terminal forming a first power supply input (Figure 5, item Cl’; i.e., upper terminal) of the device and its second terminal forming a second power supply input (Figure 5, item Cl’; i.e., lower terminal) of the device, and a pair of transistors MOS (Figure 5, items P1 and N1) switchable on command (paragraph 0007; i.e., control signals), connected between the first terminal and the second terminal of the voltage limiting circuit and having a common node (Figure 5, see common node between items P1 and N1),
a power supply output (Figure 5, item RL, paragraph 0007), and
an inductive element (Figure 5, item L) connected between the common node and the power supply output and an output capacitor (Figure 5, item CL) connected between the power supply output and the second power supply input (Figure 5, item Cl’; i.e., lower terminal).
Regarding Claim 6, Chevalier discloses wherein the switched-mode power supply device is of a buck converter type (paragraph 0006).
Regarding Claim 7, Chevalier discloses wherein the power supply output is intended to be connected to a load and the resistor of the first transistor of the voltage limiting circuit in its conducting state has a value chosen to limit the value of a current passing through the first transistor in its conducting state at a chosen percentage of a current intended to pass through the load (paragraph 0044).
Regarding Claim 13, Chevalier discloses a method for limiting an overvoltage appearing between a first terminal (Figure 5, item Cl’; i.e., upper terminal) receiving a first supply voltage from a first initial voltage (i.e., VDD) by means of a first path at least inductive (Figure 5, item CN1, paragraph 0044) and a second terminal (Figure 5, item Cl’; i.e., lower terminal) receiving a second supply voltage from a second initial voltage (i.e., ground) by means of a second path at least inductive (Figure 5, item CN2, paragraph 0044), comprising:
connecting a first MOS transistor between the first terminal and the second terminal (Figure 5, item P1, paragraph 0044).
Chevalier does not expressly disclose switching the first transistor to a conducting state when the overvoltage reaches a first value, this switching being automatically triggered by the overvoltage, and, the first transistor being conducting, limiting the overvoltage to a second value higher than the first value.
In the same field of endeavor (e.g., overvoltage limiting techniques), Childs teaches switching the first transistor to a conducting state when the overvoltage reaches a first value, this switching being automatically triggered by the overvoltage, and, the first transistor being conducting, limiting the overvoltage to a second value higher than the first value (Figure 6b, paragraphs 0040-0041; i.e., the “first value” being Vlower and the “second value” being Vupper).
The motivation discussed above with regards to Claim 1 applies equally as well to Claim 13.
Regarding Claim 14, Chevalier discloses limiting an overvoltage between a first power supply input and a second power supply input of a switched-mode power supply device respectively connected to the first terminal and to the second terminal (paragraph 0053), the first power supply input and the second power supply input connected to the first path at least inductive and the second path at least inductive receiving respectively the first initial voltage and the second initial voltage (Figure 5).
Claims 8-12 are rejected under 35 U.S.C. 103 as being unpatentable over Chevalier and Childs as applied to claim 5 above, and further in view of Telefus (U.S. Patent Application Publication Number 2022/0416681).
Regarding Claim 8, Chevalier discloses the assembly of the switched-mode power supply device of claim 5 (Figure 5).
Chevalier and Childs do not expressly disclose a processing unit comprising a module of the processing unit forming a load and capable of being powered by an output voltage delivered on the power supply output of the switched-mode power supply device.
In the same field of endeavor (e.g., overvoltage limiting techniques), Telefus teaches a processing unit comprising a module of the processing unit forming a load and capable of being powered by an output voltage delivered on the power supply output of the switched-mode power supply device (Figure 1a, item 114, paragraph 0079).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Telefus’ teachings of overvoltage limiting techniques with the teachings of Chevalier and Childs, for the purpose of expanding the capabilities of the power supply (i.e., by adding the ability to process data including power supply data).
Regarding Claim 9, Telefus teaches forming a microcontroller, the module including a digital core of the microcontroller (paragraph 0079).
Regarding Claim 10, Chevalier discloses an integrated circuit including the processing unit of claim 8 and having:
a first pad connected to the first power supply input,
a second pad connected to the second power supply input, and
a third pad connected to the common node (Figure 5, paragraph 0003; i.e., there may be plural pads on the integrated circuit to connect to the various inputs).
Regarding Claim 11, Chevalier discloses a package containing the integrated circuit of claim 10 and having:
a first pin connected to the first pad by first bonding means forming the first path at least inductive and capable of receiving the first initial voltage,
a second pin connected to the second pad by second bonding means forming the second path at least inductive and capable of receiving the second initial voltage, and
a third pin connected to the third pad by third bonding means at least inductive and capable of being connected to the inductive element (paragraph 0003; i.e., each pad has a corresponding pin on the casing).
Regarding Claim 12, Chevalier discloses a support (i.e., a casing), including the package of claim 11 and the inductive element of the switched-mode power supply device, connected to the third pin of the package, the inductive element of the switched-mode power supply device being connected to the module of the processing unit (paragraph 0003).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure because each reference discloses circuits for limiting overvoltage in an electronic system.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAISAL M ZAMAN whose telephone number is (571)272-6495. The examiner can normally be reached Monday - Friday, 8 am - 5 pm, alternate Fridays.
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/FAISAL M ZAMAN/ Primary Examiner, Art Unit 2175
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