Prosecution Insights
Last updated: July 17, 2026
Application No. 19/187,711

PIXEL, DISPLAY DEVICE, AND ELECTRONIC DEVICE INCLUDING THE SAME

Non-Final OA §103
Filed
Apr 23, 2025
Priority
Jul 03, 2024 — RE 10-2024-0087521
Examiner
ELAHI, TOWFIQ
Art Unit
2625
Tech Center
2600 — Communications
Assignee
Samsung Display Co., Ltd.
OA Round
1 (Non-Final)
79%
Grant Probability
Favorable
1-2
OA Rounds
1y 3m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allowance Rate
581 granted / 732 resolved
+17.4% vs TC avg
Moderate +15% lift
Without
With
+14.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
16 currently pending
Career history
752
Total Applications
across all art units

Statute-Specific Performance

§101
1.9%
-38.1% vs TC avg
§103
87.6%
+47.6% vs TC avg
§102
6.9%
-33.1% vs TC avg
§112
0.6%
-39.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 732 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 8, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cha (US 20210043692) in view of Piquette (US 20200388718). Regarding claim 1 Cha teaches a display device (fig. 1) comprising: a sub-pixel (fig.1, fig.4, SP) connected to a data line (fig. 4, DL); and a light sensor (fig.1, FPS) adjacent to the sub-pixel (fig.1, fig.4, SP) in a first direction and connected to a readout line ([0091] light receiving element layer PDL may be at a lower end (or a second end, e.g., a lower surface) of the second thin-film transistor layer TFTL2. An upper end (or one end, e.g., an upper surface) of the light receiving element layer PDL may face the lower end (or the other end, e.g., the lower surface) of the second thin-film transistor layer TFTL2. The light receiving element layer PDL may include light receiving elements connected to the thin-film transistors of the second thin-film transistor layer TFTL2. Each of the light receiving elements may include a first electrode, a light receiving layer, and a second electrode. In some embodiments, the light receiving layer may be an organic light receiving layer including an organic material. When the light receiving layer is an organic light receiving layer, the organic light receiving layer may combine holes and electrons by receiving the second light L2 and converting the energy of the second light L2 into an electrical signal (current or voltage) between the first electrode and the second electrode), a first element control line (fig.3, control line of TFTL1), and a second element control line (fig.3, control line of TFTL2), wherein the readout line is configured to receive a current corresponding to a light amount of light applied to the light sensor ([0091] light receiving element layer PDL may be at a lower end (or a second end, e.g., a lower surface) of the second thin-film transistor layer TFTL2. An upper end (or one end, e.g., an upper surface) of the light receiving element layer PDL may face the lower end (or the other end, e.g., the lower surface) of the second thin-film transistor layer TFTL2. The light receiving element layer PDL may include light receiving elements connected to the thin-film transistors of the second thin-film transistor layer TFTL2. Each of the light receiving elements may include a first electrode, a light receiving layer, and a second electrode. In some embodiments, the light receiving layer may be an organic light receiving layer including an organic material. When the light receiving layer is an organic light receiving layer, the organic light receiving layer may combine holes and electrons by receiving the second light L2 and converting the energy of the second light L2 into an electrical signal (current or voltage) between the first electrode and the second electrode), and Cha is silent on an area where the light sensor is formed, a third conductor configuring a portion of the readout line is between a first conductor configuring a portion of the first element control line and a second conductor configuring a portion of the second element control line. However, Piquette teaches an area where the light sensor is formed (fig. 1), a third conductor (fig.1, 116) configuring a portion of the readout line is between a first conductor (fig.1, where positive terminal of the 128 connected) configuring a portion of the first element control line and a second conductor (fig.1, 118) configuring a portion of the second element control line ([0025] also see fig. 10A, [0052]). Therefore, it would have been obvious to one of the ordinary skilled in the art to combine Cha in light of Piquette teaching so that it may include an area where the light sensor is formed, a third conductor configuring a portion of the readout line is between a first conductor configuring a portion of the first element control line and a second conductor configuring a portion of the second element control line. The motivation is to provide a light detector capable of detecting multiple colors of light. Regarding claim 8 Cha teaches a display device (fig. 1) comprising: a display panel including a plurality of sub-pixels (fig.1, SP) and a plurality of light sensors (fig.1, FPS); and a display panel driver configured to drive the display panel, wherein each of the plurality of sub-pixels is connected to the display panel driver through data lines (fig.4, 200, 300, SP, DL), each of the plurality of light sensors (fig. 5, FPS) is connected to the display panel driver (SCU) through a readout line ([0091]), a first element control line (fig.3, control line of TFTL1), and a second element control line (fig.3, control line of TFTL2), wherein the readout line is configured to receive a current corresponding to a light amount of light applied to the light sensor ([0091] light receiving element layer PDL may be at a lower end (or a second end, e.g., a lower surface) of the second thin-film transistor layer TFTL2. An upper end (or one end, e.g., an upper surface) of the light receiving element layer PDL may face the lower end (or the other end, e.g., the lower surface) of the second thin-film transistor layer TFTL2. The light receiving element layer PDL may include light receiving elements connected to the thin-film transistors of the second thin-film transistor layer TFTL2. Each of the light receiving elements may include a first electrode, a light receiving layer, and a second electrode. In some embodiments, the light receiving layer may be an organic light receiving layer including an organic material. When the light receiving layer is an organic light receiving layer, the organic light receiving layer may combine holes and electrons by receiving the second light L2 and converting the energy of the second light L2 into an electrical signal (current or voltage) between the first electrode and the second electrode), and Cha is silent on an area where the light sensor is formed, a third conductor configuring a portion of the readout line is between a first conductor configuring a portion of the first element control line and a second conductor configuring a portion of the second element control line. However, Piquette teaches an area where the light sensor is formed (fig. 1), a third conductor (fig.1, 116) configuring a portion of the readout line is between a first conductor (fig.1, where positive terminal of the 128 connected) configuring a portion of the first element control line and a second conductor (fig.1, 118) configuring a portion of the second element control line ([0025] also see fig. 10A, [0052]). Therefore, it would have been obvious to one of the ordinary skilled in the art to combine Cha in light of Piquette teaching so that it may include an area where the light sensor is formed, a third conductor configuring a portion of the readout line is between a first conductor configuring a portion of the first element control line and a second conductor configuring a portion of the second element control line. The motivation is to provide a light detector capable of detecting multiple colors of light. Regarding claim 17 Cha teaches electronic device (fig. 1) comprising: a processor ([0052] electronic (or optical) circuits, such as, for example, logic circuits, discrete components, microprocessors, to perform other functions) configured to provide input image data to a display device ([0060]); the display device configured to display an image based on the input image data ([0060]); and a power supply configured to supply power to the display device, wherein the display device comprises: a display panel including a plurality of sub-pixels and a plurality of light sensors; and a display panel driver configured to drive the display panel, each of the plurality of sub-pixels is connected to the display panel driver through data lines ([0074] The first thin-film transistor layer TFTL1 may be on the backplane BP. The first thin-film transistor layer TFTL1 may include one or more thin-film transistors for driving each of the subpixels SP. Each of the thin-film transistors of the subpixels SP may include a semiconductor layer, a gate electrode, a drain electrode, and a source electrode. In some embodiments, the first thin-film transistor layer TFTL1 may further include scan lines, data lines, power lines and scan control lines connected to the thin-film transistors of the subpixels SP and may further include routing lines connecting pads and the data lines), and a display panel driver configured to drive the display panel, each of the plurality of sub-pixels is connected to the display panel driver through data lines (fig.4, 200, 300, SP, DL), each of the plurality of light sensors (fig. 5, FPS) is connected to the display panel driver (SCU) through a readout line ([0091]), a first element control line (fig.3, control line of TFTL1), and a second element control line (fig.3, control line of TFTL2), a current corresponding to a light amount of light applied to the light sensor is transmitted to the readout line ([0091]), wherein the readout line is configured to receive a current corresponding to a light amount of light applied to the light sensor ([0091] light receiving element layer PDL may be at a lower end (or a second end, e.g., a lower surface) of the second thin-film transistor layer TFTL2. An upper end (or one end, e.g., an upper surface) of the light receiving element layer PDL may face the lower end (or the other end, e.g., the lower surface) of the second thin-film transistor layer TFTL2. The light receiving element layer PDL may include light receiving elements connected to the thin-film transistors of the second thin-film transistor layer TFTL2. Each of the light receiving elements may include a first electrode, a light receiving layer, and a second electrode. In some embodiments, the light receiving layer may be an organic light receiving layer including an organic material. When the light receiving layer is an organic light receiving layer, the organic light receiving layer may combine holes and electrons by receiving the second light L2 and converting the energy of the second light L2 into an electrical signal (current or voltage) between the first electrode and the second electrode), and Cha is silent on an area where the light sensor is formed, a third conductor configuring a portion of the readout line is between a first conductor configuring a portion of the first element control line and a second conductor configuring a portion of the second element control line. However, Piquette teaches an area where the light sensor is formed (fig. 1), a third conductor (fig.1, 116) configuring a portion of the readout line is between a first conductor (fig.1, where positive terminal of the 128 connected) configuring a portion of the first element control line and a second conductor (fig.1, 118) configuring a portion of the second element control line ([0025] also see fig. 10A, [0052]). Therefore, it would have been obvious to one of the ordinary skilled in the art to combine Cha in light of Piquette teaching so that it may include an area where the light sensor is formed, a third conductor configuring a portion of the readout line is between a first conductor configuring a portion of the first element control line and a second conductor configuring a portion of the second element control line. The motivation is to provide a light detector capable of detecting multiple colors of light. Allowable Subject Matter Claims 2-7, 9-16, 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. -Moon US 20240032806 Any inquiry concerning this communication or earlier communications from the examiner should be directed to TOWFIQ ELAHI whose telephone number is (571)270-1687. The examiner can normally be reached M-F: 10AM-3PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Boddie can be reached at (571)272-0666. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TOWFIQ ELAHI/Primary Examiner, Art Unit 2625
Read full office action

Prosecution Timeline

Apr 23, 2025
Application Filed
Apr 15, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
79%
Grant Probability
94%
With Interview (+14.6%)
2y 5m (~1y 3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 732 resolved cases by this examiner. Grant probability derived from career allowance rate.

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