Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al., US PGPUB 20230078842 hereinafter references as Kim in view of Shin et al., US PGPUB 20050264497 hereinafter references as Shin.
As to claim 1, Kim discloses a display device comprising: the first pixel includes: a (1-1)th transistor configured to control an amount of a first driving current, based on a first data voltage (e.g., transistor T1, fig. 2); and
a first additional transistor configured to receive the first data voltage from the data line, wherein the second pixel includes: a (2-1)th transistor configured to control an amount of a second driving current, based on a second data voltage (e.g., transistor T6, fig. 2);
a (2-2)th transistor configured to receive the second data voltage from the data line, wherein the (2-2)th transistor receives a (1-1)th scan signal (e.g., transistor T8, fig. 2); and
a second additional transistor configured to receive the second data voltage from the data line, wherein the second additional transistor is connected in series to the (2-2)th transistor (e.g., transistor T12, fig. 2), and
wherein a gate electrode of the first additional transistor and a gate electrode of the second additional transistor receive a same control signal, and conductivity types of the first additional transistor and the second additional transistor are different from each other (as shown in fig. 2, T6 and T12 are connected to same emission line PWElk).
Kim does not specifically disclose a first pixel and a second pixel, connected to a same data line.
However, in the same endeavor, Shin discloses a first pixel and a second pixel, connected to a same data line (as shown in fig. 1, at least two pixels sharing one of the data lines).
Therefore, it would have been obvious to one of ordinary skill in the art to modify the disclosure of Kim to further include Shin’s pixels and data lines arrangement in order to increase a display active area.
As to claim 20, Kim discloses a n electronic device comprising: a timing controller configured to receive grayscales for an input image from a processor (e.g., timing controller 300, fig. 1);
a data driver configured to provide data voltages to data lines, based on the grayscales (e.g., source driver 200, fig. 1);
a scan driver configured to provide scan signals to scan lines (e.g., scan driver 110, fig. 1);
a control scan driver configured to provide control signals to control lines ([0042] FIG. 9 is a waveform diagram showing a scan initialization signal, a scan write signal, a scan control signal); and
a display panel including a plurality of pixels connected to the data lines, the scan lines, and the control lines (display panel 100, fig. 1),
wherein the display panel includes a first pixel and a second pixel, connected to a same data line among the data lines,
wherein the first pixel includes: a (1-1)th transistor configured to control an amount of a first driving current, based on a first data voltage (e.g., transistor T1, fig. 2); and
a first additional transistor configured to receive the first data voltage from the data line (e.g., transistor T6, fig. 2),
wherein the second pixel includes: a (2-1)th transistor configured to control an amount of a second driving current, based on a second data voltage (e.g., second pixel driver PDU2, fig. 2);
a (2-2)th transistor configured to receive the second data voltage from the data line, wherein the (2-2)th transistor receives a (1-1)th scan signal (e.g., transistor T8, fig. 2); and
a second additional transistor configured to receive the second data voltage from the data line, wherein the second additional transistor is connected in series to the (2-2)th transistor (e.g., transistor T12, fig. 2), and
wherein a gate electrode of the first additional transistor and a gate electrode of the second additional transistor receive a same control signal, and conductivity types of the first additional transistor and the second additional transistor are different from each other (as shown in fig. 2, T6 and T12 are connected to same emission line PWElk).
Kim does not specifically disclose a first pixel and a second pixel, connected to a same data line.
However, in the same endeavor, Shin discloses a first pixel and a second pixel, connected to a same data line (as shown in fig. 1, at least two pixels sharing one of the data lines).
Therefore, it would have been obvious to one of ordinary skill in the art to modify the disclosure of Kim to further include Shin’s pixels and data lines arrangement in order to increase a display active area.
As to claim 2, the combination of Kim and Shin discloses the display device of claim 1. The combination further discloses a voltage level of the same control signal is changed during a period in which the (1-1)th scan signal having a turn-on level is received (Kim, [0101] The first transistor T1 controls the control current flowing to a third node N3 of the third pixel driver PDU3 in response to the voltage applied to a gate electrode of the first transistor T1).
As to claim 3, the combination of Kim and Shin discloses the display device of claim 1. The combination further discloses the first pixel further includes a (1-2)th transistor configured to receive the first data voltage from the data line, wherein the (1-2)th transistor is connected in series to the first additional transistor (Kim, e.g., transistor T6, fig. 2).
As to claim 4, the combination of Kim and Shin discloses the display device of claim 1. The combination further discloses a first electrode of the first additional transistor is connected between the (2-2)th transistor and the second additional transistor (Kim, e.g., T6 and T8 are connected through T15, as shown in fig. 2).
As to claim 5, the combination of Kim and Shin discloses the display device of claim 1. The combination further discloses a plurality of scan drivers, wherein the plurality of scan drivers include a first scan driver configured to output the (1-1)th scan signal and a control scan driver configured to output the same control signal, wherein a number of scan stages included in each of the first scan driver and the control scan driver is N, wherein a number of scan stages included in each of the other scan drivers except the first scan driver and the control scan driver among the plurality of scan drivers is M, and wherein M is an integer greater than 0, and N is an integer greater than M (Kim, [0042] FIG. 9 is a waveform diagram showing a scan initialization signal, a scan write signal, a scan control signal, a PWM emission signal, a PAM emission signal, and a sweep signal applied to sub-pixels disposed on k.sup.th to (k+5).sup.th row lines in the N.sup.th frame period).
As to claim 6, the combination of Kim and Shin discloses the display device of claim 1. The combination further discloses a plurality of scan drivers, wherein the plurality of scan drivers include a first scan driver configured to output the (1-1)th scan signal, wherein a number of scan stages included in the first scan driver is N, wherein a number of scan stages included in each of the other scan drivers except the first scan driver among the plurality of scan drivers is M, and wherein M is an integer greater than 0, and N is an integer greater than M (Kim, [0042] FIG. 9 is a waveform diagram showing a scan initialization signal, a scan write signal, a scan control signal, a PWM emission signal, a PAM emission signal, and a sweep signal applied to sub-pixels disposed on k.sup.th to (k+5).sup.th row lines in the N.sup.th frame period).
As to claim 7, the combination of Kim and Shin discloses the display device of claim 6. The combination further discloses a third pixel and a fourth pixel, connected to the data line, wherein the third pixel includes: a (3-1)th transistor configured to control an amount of a third driving current, based on a third data voltage; and a third additional transistor configured to receive the third data voltage from the data line, wherein the fourth pixel includes: a (4-1)th transistor configured to control an amount of a fourth driving current, based on a fourth data voltage; a (4-2)th transistor configured to receive the fourth data voltage from the data line, wherein the (4-2)th transistor receives a (1-2)th scan signal; and a fourth additional transistor configured to receive the fourth data voltage from the data line, wherein the fourth additional transistor is connected in series to the (4-2)th transistor, and wherein a gate electrode of the third additional transistor and a gate electrode of the fourth additional transistor receive the same control signal, and conductivity types of the third additional transistor and the fourth additional transistor are different from each other (Shin, [0079] While two pixels are provided in a pixel area and a frame is divided into two fields in the above exemplary embodiments, three pixels may be provided in a pixel area and a frame may be divided into three fields in another exemplary embodiment).
As to claim 8, the combination of Kim and Shin discloses the display device of claim 7. The combination further discloses conductivity types of the first additional transistor and the fourth additional transistor are the same as each other, and wherein conductivity types of the second additional transistor and the third additional transistor are the same as each other (Shin, The display device of claim 7, wherein a third pixel of the first side and a fourth pixel of the second side are formed in a second pixel area of the pixel areas, wherein the third pixel of the first side is formed with a second even scan line of the second and third scan lines, and wherein the fourth pixel of the second side is formed with a second odd scan line of the second and third scan lines, Claim 8).
As to claim 9, the combination of Kim and Shin discloses the display device of claim 7. The combination further discloses a period in which the (1-1)th scan signal having a turn-on level is received and a period in which the (1-2)th scan signal having a turn-on level is received are different from each other, wherein a voltage level of the same control signal is primarily changed during the period in which the (1-1)th scan signal having the turn-on level is received, and wherein the voltage level of the same control signal is secondarily changed during the period in which the (1-2)th scan signal having the turn-on level is received (Kim, During the turn-on period of the fourth transistor T4, the first transistor T1 may operate as a diode. The fifth transistor T5 is turned-on by a k.sup.th PWM emission signal of a k.sup.th PWM emission line PWELk to connect the first electrode of the first transistor T1 to a first power line VDL1. The sixth transistor T6 is turned-on by the k.sup.th PWM emission signal of the k.sup.th PWM emission line PWELk to connect the second electrode of the first transistor T1 to the third node N3 of the third pixel driver PDU3).
As to claim 10, the combination of Kim and Shin discloses the display device of claim 7. The combination further discloses the third pixel further includes a (3-2)th transistor configured to receive the third data voltage from the data line, wherein the (3-2)th transistor is connected in series to the third additional transistor (Kim, [0104] The third pixel driver PDU3 may include fifteenth to seventeenth transistors T15 to T17, a nineteenth transistor T19, and a third capacitor C3).
As to claim 11, the combination of Kim and Shin discloses the display device of claim 7. The combination further discloses a first electrode of the third additional transistor is connected between the (4-2)th transistor and the fourth additional transistor (Kim, [0125] The fourth transistor T4 is turned-on by the k.sup.th scan write signal of the k.sup.th scan write line GWLk to connect the gate electrode and the second electrode of the first transistor T1).
As to claim 12, the combination of Kim and Shin discloses the display device of claim 1. The combination further discloses the first pixel further includes a (1-1)th emission transistor configured to allow the first driving current to flow therethrough in case that a (1-1)th emission signal having a turn-on level is received, wherein the second pixel further includes a (2-1)th emission transistor configured to allow the second driving current to flow therethrough in case that the (1-1)th emission signal having the turn-on level is received, wherein the same control signal is a (1-2)th emission signal, and wherein the (1-1)th emission signal has a phase delayed from a phase of the (1-2)th emission signal (Kim, [0101] The fifth transistor T5 is turned-on by a k.sup.th PWM emission signal of a k.sup.th PWM emission line PWELk to connect the first electrode of the first transistor T1 to a first power line VDL1).
As to claim 13, the combination of Kim and Shin discloses the display device of claim 12. The combination further discloses the first pixel further includes a (1-2)th emission transistor configured to allow the first driving current to flow therethrough in case that a second emission signal having a turn-on level is received, and wherein the second pixel further includes a (2-2)th emission transistor configured to allow the second driving current to flow therethrough in case that the second emission signal having the turn-out level is received (Kim, [0103] The twelfth transistor T12 is turned-on by the k.sup.th PWM emission signal of the k.sup.th PWM emission line PWELk to connect the first electrode of the eighth transistor T8 to a second power line VDL2).
As to claim 14, the combination of Kim and Shin discloses the display device of claim 13. The combination further discloses a first emission driver configured to output the (1-1)th emission signal and the (1-2)th emission signal; and
a second emission driver configured to output the second emission signal, wherein a number of emission stages included in the first emission driver is P, wherein a number of emission stages included in the second emission driver is Q, and wherein Q is an integer greater than 0, and P is an integer greater than Q (Kim, e.g., an emission and sweep signal output unit 113, and an emission signal output unit 114).
As to claim 15, the combination of Kim and Shin discloses the display device of claim 13. The combination further discloses a gate electrode of the (2-1)th transistor is connected to a first node, a first electrode of the (2-1)th transistor is connected to a second node, and a second electrode of the (2-1)th transistor is connected to a third node, wherein the (2-2)th transistor and the second additional transistor are connected between the data line and the first node, wherein the (2-1)th emission transistor is connected between the third node and a fourth node, and
wherein the (2-2)th emission transistor is connected between the second node and a first power line (Kim, [0103] The ninth transistor T9 is turned-on by the k.sup.th scan write signal of the k.sup.th scan write line GWLk to supply the first PAM data voltage of the first PAM data line RDL to the first electrode of the eighth transistor T8. The tenth transistor T10 is turned-on by the k.sup.th scan control signal of the k.sup.th scan control line GCLk to supply the k.sup.th scan control signal to the gate electrode of the eighth transistor T8).
As to claim 16, the combination of Kim and Shin discloses the display device of claim 15. The combination further discloses the second pixel further includes: a light emitting element including an anode electrode connected to the fourth node;
a (2-3)th transistor connected between the first node and a reference voltage line; a (2-4)th transistor connected between the fourth node and an initialization voltage line; a first capacitor connected between the first node and the third node; and a second capacitor connected between the first power line and the third node (Kim, [0118] The first electrode of the light emitting element EL may be an anode electrode and the second electrode thereof may be a cathode electrode. The light emitting element EL may be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode).
As to claim 17, the combination of Kim and Shin discloses the display device of claim 1. The combination further discloses a gate electrode of the (2-1)th transistor is connected to a first node, a first electrode of the (2-1)th transistor is connected to a second node, a second electrode of the (2-1)th transistor is connected to a third node, and a body of the (2-1)th transistor is connected to a fourth node, and wherein the (2-2)th transistor and the second additional transistor are connected between the data line and the fourth node (Kim, [0122] The second transistor T2 is turned-on by the k.sup.th scan write signal of the k.sup.th scan write line GWLk to supply the data voltage of the j.sup.th data line DLj to the first electrode of the first transistor T1. The gate electrode of the second transistor T2 may be connected to the k.sup.th scan write line GWLk, the first electrode thereof may be connected to the j.sup.th data line DLj, and the second electrode thereof may be connected to the first electrode of the first transistor T1).
As to claim 18, the combination of Kim and Shin discloses the display device of claim 17. The combination further discloses the second pixel further includes: a light emitting element including an anode electrode connected to the third node; a (2-3)th transistor connected between the fourth node and a reference voltage line; and
a (2-4)th transistor connected between the fourth node and an initialization voltage line (Kim, [0118] The first electrode of the light emitting element EL may be an anode electrode and the second electrode thereof may be a cathode electrode. The light emitting element EL may be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode).
As to claim 19, the combination of Kim and Shin discloses the display device of claim 18. The combination further discloses the second pixel further includes: a (2-5)th transistor connected between a first power line and the second node; a (2-6)th transistor connected between the first power line and the first node; and a (2-7)th transistor connected between the first node and the second node, wherein a gate electrode of the (2-7)th transistor receives a (2-1)th scan signal, wherein the same control signal is a (2-2)th scan signal, and wherein the (2-2)th scan signal has a phase delayed from a phase of the (2-1)th scan signal (Kim, [0022] The first pixel driver may further include a fifth transistor configured to apply the first data voltage of the first data line to the first electrode of the first transistor according to the second scan signal, a sixth transistor configured to apply an initialization voltage of an initialization voltage line to the gate electrode of the first transistor according to the third scan signal, and a seventh transistor configured to connect the gate electrode and a second electrode of the first transistor according to the second scan signal).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim et al., US PGPUB 20230206844 discloses a pixel circuit and a display device including the same are disclosed. The pixel circuit includes: a driving transistor which includes a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node, and supplies a driving current to a light emitting device; a first transistor that is electrically connected between the first node and the second node; a second transistor that is electrically connected between the first node and a data voltage; a third transistor that is electrically connected between the first node and a power supply line that supplies a high potential voltage; and a storage capacitor that includes a first electrode connected to the high potential voltage and a second electrode connected to the second node.
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/SAHLU OKEBATO/Primary Examiner, Art Unit 2625 2/14/2026