DETAILED ACTIONNotice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over JEONG et al (2008/0252504) (herein “JEONG”) in view of CHOI et al (2015/0179125) (herein “CHOI”). In regards to claims 1 and 8, JEONG teaches a display system comprising: a display panel (See; p[0004] for LCD panel); a data driver configured to output a data voltage to the display panel (See; p[0005] for column driver connected to data lines driving pixels), the data driver comprising: an offset storer (See; Fig. 1, p[0011] and claim 4 for storing the offset voltage data for each n channel in a memory 140); and an offset compensator (See; Fig. 1, claim 4, p[0014], p[0022] for compensating for the offset at subtracting unit 150); and an offset apparatus including an offset measurer configured to receive a sensing voltage from the data driver and to measure offsets of output amplifiers of the data driver (See; p[0031] for measuring an offset voltage for each channel. See p[0020]-p[0021] where this is initiated by the controller initiating a test mode), wherein the offset storer is configured to store the offsets of the output amplifiers (See; p[0011], p[0024] and claim 4 for storing the offset voltage data for each n channel in a memory), and the offset compensator is configured to receive the offsets of the output amplifiers and to compensate a data signal (See; Fig. 1, claim 4, p[0014], p[0022], p[0024]-p[0025] for compensating for the offset from the amplifiers 110). JEON fails to explicitly teach an offset apparatus disposed outside the data driver. However, CHOI teaches an offset apparatus disposed outside the data driver (See; Fig. 2 where the offset adjusting circuit 120 is disposed outside the data driver 101a). Therefore it would have been obvious to one of ordinary skill in the art at the time of filing to modify JEONG to have an offset apparatus outside the data driver as a mere design choice based on optimal circuit layout for the given device. In regards to claim 2, JEONG teaches wherein the offset measurer is configured to measure the offsets of all of the output amplifiers of the data driver (See; p[0031] for measuring an offset voltage for each channel), and wherein the offset storer is configured to store the offsets of all of the output amplifiers of the data driver (See; p[0011], p[0024] and claim 4 for storing the offset voltage data for each n channel in a memory).
In regards to claim 3, JEONG teaches wherein the offset apparatus further comprises: an offset determiner configured to receive the offsets of the output amplifiers from the offset measurer and determine whether the offsets are outside a predetermined tolerance range (See; Fig. 1 and p[0024]-p[0026] for comparator 130 which compares the measured offsets to a reference voltage to determine which individual channels need compensated).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over JEONG et al (2008/0252504) (herein “JEONG”) in view of CHOI et al (2015/0179125) (herein “CHOI”) and further in view of HA et al (2022/0383806) (herein “HA”). In regards to claims 5 and 13, JEONG teaches wherein the data driver further comprises: a digital-to-analog converting circuit configured to convert the compensated data signal to the data voltage having an analog type (See; Fig. 1 for 8-bit R string DAC); and an output amplifying circuit configured to output the data voltage to the display panel (See; Fig. 1 for amplifiers 110), wherein the offset compensator is configured to output the compensated data signal to the DAC, and wherein the offset measurer is configured to receive the sensing voltage from the output amplifying circuit (See; Fig. 1). JEONG fails to explicitly teach wherein the data driver further comprises: a shift register configured to receive a compensated data signal; a latch configured to temporally store the compensated data signal. However, JEONGS data driver and 8-bit R-string 16 channel DAC would commonly have an internal shift register acting as a serial-in, parallel-out register and on-chip data latches for each channel to hold the respective output voltages while other channels are being updated via the shared input bus. However, for the sake of compact prosecution, Ha is introduced to teach a well-known data driver having a shift register; latch; DAC and an output amplifying circuit (See; Fig. 6 for a typical data driver stack 140 having a shift register, latch, DAC and amplifier sections). Therefore I would have been obvious to one of ordinary skill in the art at the time of filing to modify JEONG’s 8-bit R-string 16 channel DAC to have a shift register and latch as is commonly used in data drivers for optimal performance of the data driver.
Claim(s) 6 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over JEONG et al (2008/0252504) (herein “JEONG”) in view of CHOI et al (2015/0179125) (herein “CHOI”) and further in view of HE et al (2024/0013745) (herein “HE”). In regards to claim 6, JEONG teaches wherein the data driver further comprises: a first output amplifier; a second output amplifier; a first data line; a second data line (See; Fig. 1); an 1-1 switch disposed between the first output amplifier and the first data line and a 2-2 switch disposed between the second output amplifier and the second data line (See; Fig. 1 for T0 and T1). JEONG fails to explicitly teach; an 1-2 switch disposed between the first output amplifier and the second data line; a 2-1 switch disposed between the second output amplifier and the first data line. However, HE teaches wherein the data driver further comprises: a first output amplifier; a second output amplifier; a first data line; a second data line; an 1-1 switch disposed between the first output amplifier and the first data line; an 1-2 switch disposed between the first output amplifier and the second data line; a 2-1 switch disposed between the second output amplifier and the first data line; and a 2-2 switch disposed between the second output amplifier and the second data line (See; Fig. 3C for amplifiers 1023a, 1023b and switches T11, T21, T12 and T22 connected to data lines DL1 and DL2). Therefore it would have been obvious to one of ordinary skill in the art at the time of filing to modify JEONG to have cross data line switches such as in HE so as to allow different voltages to be fed to different data lines from different amplifiers during different modes to improve display image quality. In regards to claim 7, HE teaches wherein the first output amplifier is connected to the first data line and the second output amplifier is connected to the second data line in a first mode, wherein the first output amplifier is connected to the second data line and the second output amplifier is connected to the first data line in a second mode, and wherein the first mode and the second mode alternately operate (See; Fig. 3C, p[0030] where different modes are enacted by signal lines SEL1 and SEL2. See Fig. 4 and p[0038]-p[0039] where SE 1 and SE 2 (corresponding to SEL1 and SEL2) are alternately operated).
Claim(s) 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over JEONG et al (2008/0252504) (herein “JEONG”) in view of SERIZAWA et al (2022/0121032) (herein “SERIZAWA”) and further in view of CHOI et al (2015/0179125) (herein “CHOI”).
In regards to claim 16, JEONG teaches a display system comprising: a first display panel (See; p[0004] for LCD panel); See; p[0005] for column driver connected to data lines driving pixels); , at least one of the first data driver See; Fig. 1, p[0011] and claim 4 for storing the offset voltage data for each n channel in a memory 140); and an offset compensator (See; Fig. 1, claim 4, p[0014], p[0022] for compensating for the offset at subtracting unit 150); a first offset apparatus configured to receive a first sensing voltage from the first data driver and to measure a first offset of a first output amplifier of the first data driver (See; p[0031] for measuring an offset voltage for each channel. See p[0020]-p[0021] where this is initiated by the controller initiating a test mode); See; p[0011], p[0024] and claim 4 for storing the offset voltage data for each n channel in a memory) See; Fig. 1, claim 4, p[0014], p[0022], p[0024]-p[0025] for compensating for the offset from the amplifiers 110). JEONG fails to teach a first and second display. However, SERIZAWA teaches a first and second display (See; Fig. 1A, 2 and p[0106] for a first display panel 39L and second display panel 39R). Therefore it would have been obvious to one of ordinary skill in the art at the time of filing to modify JEONG to have two displays so as to be have JEONGS offset compensation operable in a head mounted display arrangement such as in SERIZAWA. The combination further fails to explicitly teach a second data driver configured to output a second data voltage to the second display panel, and the second data driver comprising: an offset storer and a second offset apparatus configured to receive a second sensing voltage from the second data driver and to measure a second offset of a second output amplifier of the second data driver, wherein the offset storer is configured to store the second offset of the second output amplifier and the offset compensator is configured to the second offset of the second output amplifier and to compensate a second data signal. However, the Examiner contends that this recitation of a second display having a second data driver and a second output amplifier, a second offset storer and second offset compensator is a mere duplication of parts. Claim 16 is merely duplicating claim 1 (a one display system) to operate on two displays. Therefore it would have been obvious to one of ordinary skill in the art at the time of filing to modify JEONG’s display offset compensation to work with multiple displays such as in SERIZAWA as a mere duplication of parts (See; MPEP 2144.04 VI B ( In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960))). Further, JEON fails to explicitly teach the first and second offset apparatus disposed outside the first and second data driver. However, CHOI teaches an offset apparatus disposed outside the data driver (See; Fig. 2 where the offset adjusting circuit 120 is disposed outside the data driver 101a). Therefore it would have been obvious to one of ordinary skill in the art at the time of filing to modify JEONG and SERIZAWA to have the first and second offset apparatus outside the data drivers as a mere design choice based on optimal circuit layout for the given device. In regards to claim 17, SERIZAWA teaches further comprising: a first driving controller configured to output the first data signal to the first data driver; and a second driving controller configured to output the second data signal to the second data driver (See; FIG. 2 and p[0106] for a first and second drive circuit 38L / 38R and first and second driving controllers 37R and 37L).
In regards to claim 18, SERIZAWA teaches further comprising: a driving controller configured to output the first data signal to the first data driver and the second data signal to the second data driver (See; Fig. 2 and p[0109] for signal processing circuit 92). In regards to claim 19, SERIZAWA teaches wherein the first display panel is a first-eye display panel corresponding to a first eye of a user, and wherein the second display panel is a second-eye display panel corresponding to a second eye of the user (See; Figs. 1A, 1B, 2).
In regards to claim 20, SERIZAWA teaches a first-eye lens corresponding to the first-eye display panel; and a second-eye lens corresponding to the second-eye display pane (See; Figs. 1A, 1B, 2 for lens 40 on each eye).
Allowable Subject Matter
Claims 8 and 12-15 are allowed.
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN A BOYD whose telephone number is (571)270-7503. The examiner can normally be reached Mon - Fri 8:00 - 5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at (571) 272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JONATHAN A BOYD/Primary Examiner, Art Unit 2627
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