DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the body electrode of the first transistor connected to the source electrode of the first transistor must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 7-9, 12, 15-16, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2019/0371231) in view of Kim et al. (US 2024/0256061, hereinafter Kim061), further in view of further in view of Yang et al. (US 2019/0172396).
As to Claim 1, Kim et al. A display device comprising a sub-pixel, wherein the sub-pixel comprises: a first transistor (fig.8, transistor 325) including a gate electrode connected to a first node (fig.8, node at gate of transistor 325), a source electrode connected to a first power line to which a first power voltage is applied (fig.8, electrode of transistor 325 connected to VDD), a body electrode connected to the source electrode, and a drain electrode connected to a second node (fig.8, node at drain of transistor 325);
a second transistor (fig.8, transistor 336) that switches an electrical connection between a third node (fig.8, node at drain of transistor 336 (connected to capacitor 334)) and a data line (fig.8, data line 5 Data) and including a gate electrode electrically connected to a first sub-scan line (fig.8, gate of transistor 336 connected to control signal SPWM);
a third transistor (fig.8, transistor 331) connected to the first node (fig.8, electrode of transistor 331 connected to node at gate of transistor 325) and including a gate electrode connected to the third node (fig.8, gate of transistor 331 connected to node at drain of transistor 336; para.0127),
a fourth transistor that switches an electrical connection between the first node and the second node and including a gate electrode connected to a second sub-scan line,
a first capacitor including a first electrode electrically connected to the first node and a second electrode connected to a second power line to which a second power voltage is applied (fig.8, capacitor 312 connected to node at of transistor 325 and VDD)
a second capacitor including a first electrode electrically connected to the third node and a second electrode connected to a sweep line to which a sweep signal is applied (fig.8, electrode of capacitor 335 connected to node drain of transistor 336 and sweep line Sweep); and
a light emitting element connected between the second node and a third power line to which a third power voltage is applied (fig.8 light-emitting element 200 connected between second node and VSS).
Kim et al. does not expressly disclose a first transistor including a body electrode connected to the source electrode; a fourth transistor that switches an electrical connection between the first node and the second node and including a gate electrode connected to a second sub-scan line; a first capacitor including a second electrode connected to a second power line to which a second power voltage is applied.
Kim061 discloses a first transistor including a body electrode connected to the source electrode (fig.2, back-gate of transistor DRT connected to source node N4), a fourth transistor that switches an electrical connection between the first node and the second node and including a gate electrode connected to a second sub-scan line (fig.2, transistor T2 connected between node N2 at gate of transistor DRT and second node N3 drain of transistor DRT and a gate connected to scan Scan2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kim et al. with the teachings of Kim061., the motivation being to provide stable current output of the driving transistor and compensation for threshold voltage of the driving transistor.
Kim et al. in view of Kim061 do not expressly disclose where a first capacitor including a second electrode connected to a second power line to which a second power voltage is applied.
Yang et al. discloses a capacitor including a second electrode connected to a second power line to which a second power voltage is applied (fig.2, capacitor Cst connected to node N1 and Vnit; para.0059,0082).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Kim et al. in view of Kim061, with the teachings of Yang et al., to provide a storage capacitor that may store node voltage at gate of the driving transistor based in initialization voltage.
As to Claim 2, Kim et al. in view of Kim061 disclose, as modified by Yang et al. wherein the first power voltage has one of a low level, a middle level, and a high level (Kim-fig.3,9, driving voltage VDD; para.0122; Yang-fig.3, para.0060; ELVDD, has low, middle, high level, ELVDDL,ELVDDM,ELVDDH, respectively).
As to Claim 7, Kim et al. in view of Kim061, as modified by Yang et al. disclose wherein in case that a first scan signal of a turn-on level is applied to the first sub-scan line, the third node and the data line are electrically connected (Kim-fig.8, transistor 336 is turned on in response to SPWM; para.0127).
As to Claim 8, Kim et al. in view of Kim061, as modified by Yang et al., disclose wherein in a period in which the third power voltage transits from a high level to a low level and a voltage level of the sweep signal decreases from a high level to a low level (fig.9, light emission period VSS is low and sweep signal decreases to low level), in case that a voltage of a turn-on level is applied to the third transistor, the first transistor is turned off (Kim-para.0157-0158).
As to Claim 9, Kim et al. in view of Kim061, as modified by Yang et al., disclose wherein the sub-pixel emits light having luminance according to a duration of time in which a driving current flows in a direction from the first transistor to the light emitting element (Kim-fig.8-9; para.0012,0102,0155).
As to Claim 12, Kim et al. in view of Kim061, as modified by Yang et al., disclose wherein each of the first transistor, the third transistor, and the fourth transistor includes a P-type semiconductor (Kim-fig.8).
As to Claim 15, Kim et al. in view of Kim061, as modified by Yang et al., disclose a display panel in which a plurality of sub-pixels including the sub-pixel are disposed (Kim-fig.12; Yang-fig.1); a gate driver that supplies a first scan signal and a second scan signal to the plurality of sub-pixels (Kim-fig.12, gate driver 830; Yang-fig.1); a sweep supply circuit that supplies the sweep signal to the plurality of sub-pixels; a data driver that supplies a data voltage to the plurality of sub-pixels (Kim-fig.7-8,12, driving circuit 300; para.0178); and a voltage generator that supplies the first power voltage, the second power voltage, and the third power voltage to the plurality of sub-pixels (Kim-fig.8; Yang-fig.1, voltage generator 170).
As to Claim 16, Kim et al. in view of Kim061, as modified by Yang et al., disclose wherein the voltage generator is supplied with a driving voltage, a ground voltage, and a voltage control signal, and the voltage generator outputs the first power voltage having one of a low level, a middle level, and a high level in response to the voltage control signal (Yang-fig.1,3; voltage generator 170, control signal 107c; para.0046,0058-0060).
As to Claim 20 has limitations similar to those of Claims 1,15-16 and are met by the references as set forth above. Claim 20 further recites: a processor that transmits input image data (see Kim-fig.12-processor; Yang-fig.1-controller 100)
Claim(s) 10-11,13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US S2019/0371231) in view of Kim et al. (US 2024/0256061, hereinafter Kim061), further in view of further in view of Yang et al. (US 2019/0172396), and further in view of Tsuboi et al. (US 2020/0143741).
As to Claim 10, Kim et al. in view of Kim061, as modified by Yang et al., disclose wherein the third transistor is connected between the first power line and the first node (Kim-fig.8, transistor 331 connected between VDD and node at gate of transistor 325).
Kim et al. in view of Kim061, as modified by Yang et al. do not expressly disclose where third transistor includes a body electrode connected to the first power line.
Tsuboi et al. discloses a pixel circuit comprising transistors including a body electrode connected to a first power line (fig.2-3,9; power potential 208 Vdd is applied to back gate of transistors; para.0041).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Kim et al. in view of Kim061, as modified by Yang et al., with the teachings of Tsuboi et al., the motivation being to control the light emission of the organic light emitting element.
As to Claim 11, Kim et al. in view of Kim061, as modified by Yang et al. disclose wherein the third transistor is connected between the second power line and the first node (Kim-fig.8, transistor 331 connected between VDD and node at gate of transistor 325; Yang-fig.2, Vinit).
Kim et al. in view of Kim061, as modified by Yang et al. do not expressly disclose third transistor includes a body electrode connected to the first power line.
Tsuboi et al. discloses a pixel circuit comprising transistors including a body electrode connected to a first power line (fig.2-3,9; power potential 208 Vdd is applied to back gate of transistors; para.0041).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Kim et al. in view of Kim061, as modified by Yang et all, with the teachings of Tsuboi et al., the motivation being to control the light emission of the organic light emitting element
As to Claim 13, Kim et al. in view of Kim061, as modified by Yang et al. and Tsuboi et al. disclose wherein the second transistor includes a P-type semiconductor, and includes a body electrode connected to the second power line (Kim-fig.8, transistor 336; Yang-fig.2-3; Tsuboi-fig.2).
As to Claim 14, Kim et al. in view of Kim061, as modified by Yang et al. and Tsuboi et al. disclose wherein the second transistor includes an N-type semiconductor, and includes a body electrode connected to a fourth power line (Kim-fig.11-transistor 336; Yang-figs.2-3; Tsuobi-fig.2, para.0039).
Allowable Subject Matter
Claims 17-19 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: Claim 17 is allowable over the prior art of record for the reasons noted in OA 02/25/2026.
Claims 3-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Claim 3 is allowable over the prior art of record for the reasons noted in OA 02/25/2026.
Response to Arguments
Applicant's arguments filed 05/15/2026 have been fully considered but they are not persuasive.
Re the objection to the drawings, applicant argues “Applicant refers to FIG. 5 of the present application as originally filed (reproduced below), which shows both the source electrode and the body electrode of the first transistor TR1 are electrically connected to the second power line PL2 (VDD2). Accordingly, Applicant submits that the drawings as originally filed show all features of the claims. Applicant therefore requests that the objections to the drawings be withdrawn.”
However, the examiner respectfully disagrees. As depicted in Fig. 5, the source electrode of the first transistor is connected to first power line (PL2) and the body electrode of the first transistor is connected to the first power line (PL2). However, it does not show the source being connected to the body electrode. In the specification as filed, this feature is described: [0111] In the embodiment, the source electrode and the body electrode of the first transistor TR1 may be electrically connected to each other and may be commonly connected to the second power line PL2”.
Since this particular feature of this embodiment is being claimed, it should also be shown in the drawings.
Re the 103 rejection, applicant argues “Kim et al. does not disclose that the alleged second transistor 336 connects the data line Data and the alleged third node/gate of alleged third transistor 331 due to the presence of capacitor 334. That is, the gate electrode of transistor 331 is not electrically connected to the third node. Therefore, Kim et al. does not disclose a configuration corresponding to "a third transistor ... including a gate electrode connected to the third node," as recited in claims.
However, the examiner respectfully disagrees.
The claim limitation reads in part “a second transistor that switches an electrical connection between a third node and a data line and including a gate electrode electrically connected to a first sub-scan line; a third transistor connected to the first node and including a gate electrode connected to the third node”
In Kim et al. in view of Kim061, as modified by Yang et al., Kim et al. discloses transistor 336 (read as second transistor) that includes a source terminal connected to data line 5 and drain terminal connected to a first terminal of capacitor 335 and of capacitor 335 (read third node) (para.0125); transistor 331 (read as third transistor) including a terminal connected to a node at source terminal of transistor 325 (first node) and a gate of transistor 331 is connected to the third node (node at drain terminal of transistor 336) via capacitor 334.
Kim et al. discloses [127] A gate terminal voltage of the fourth transistor 331 may be a voltage based on a threshold voltage of the fourth transistor 331 while the fifth transistor 332 is turned on. Thereafter, while the seventh transistor 336 is turned on according to a control signal (SPWM(n)), when a pulse width setup voltage (PWM data) is input through the data line 5, the gate terminal voltage of the fourth transistor 331 may be a voltage based on the threshold voltage and pulse width setup voltage of the fourth transistor 331, and thereafter, when a linearly shifting sweep signal is input through one terminal of the third capacitor 335, the gate terminal voltage of the fourth transistor 331 may be linearly shifted according to the sweep signal.
Although, the gate of transistor 331 is not directly connected to the third node, it is connected to the third node via capacitor 334.
Therefore, In Kim et al. in view of Kim061, as modified by Yang et al., disclose the limitations as claimed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892 form.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DISMERY E. MERCEDES whose telephone number is (571)272-7558. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at 571-272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DISMERY MERCEDES/Primary Examiner, Art Unit 2627
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