Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
1. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Vorbach et al (US 2015/0106596, herein Vorbach) in view of Goudie et al (US 2022/0114016, herein Goudie).
Regarding claim 1, Vorbach teaches a reconfigurable processor ([0007], [0334], reconfigurable architecture) comprising:
a pipelined processor and memory modules associated with the pipelined processor, the pipelined processor being configured to execute an instruction set in a multi-stage pipeline including an instruction fetch (IF) stage, an instruction decode (ID) stage and an execute (EX) stage (Fig 9 & [0250], [0331], pipelined processor, [0453], [0459], fetch stage, [0149], claims 2-3, decoder stage, [0453-0454], execute stage),
wherein the pipelined processor is further adapted to perform each of the IF, ID and EX stages as two or more threads in a multi-thread mode and to share an IF pipeline output of the IF stage and/or an ID pipeline output of the ID stage between the two or more threads ([0053], [0194], multithreaded execution mode, [0149], [0389-0390], [0459], claims 1-2, sharing front-end pipeline stages and memory between threads in the multithreaded mode).
Vorbach fails to teach wherein the threads are interleaved.
Goudie teaches a reconfigurable processor comprising a pipelined processor ([0014], [0113], reconfigurable pipelined processor) configured to perform operations as two or more interleaved threads in a multi-thread mode ([0044], interleaving plurality of threads throughout processor units).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Vorbach and Goudie to utilize thread interleaving. While Vorbach does not explicitly state that different stages of thread operations may be explicitly “interleaved”, one of ordinary skill in the art would understand that simultaneous multithreading, described by Vorbach, may result in the sharing of processor resources in an interleaved fashion. As both Vorbach and Goudie disclose reconfigurable parallel processors that operate in multithreaded execution modes, the combination would merely entail a simple substitution of known prior art elements to achieve predictable results.
Regarding claim 2, the combination of Vorbach and Goudie teaches the reconfigurable processor of claim 1, further comprising bypass registers adapted to allow the pipelined processor to switch between performing the IF, ID and EX stages in a single-thread mode and performing the IF, ID and EX stages in the multi-thread mode (Vorbach Fig 9, [0159], [0223-0225], [0337], registers for using and forwarding data, [0030], execution modes to enable multithreading).
Regarding claim 3, the combination of Vorbach and Goudie teaches the reconfigurable processor of claim 1, further comprising: one or more further pipelined processors and further memory modules for each of the one or more further pipelined processors, each of the one or more further pipelined processors being configured to execute the instruction set in a further multi-stage pipeline including a further IF stage, a further ID stage and a further EX stage, wherein the memory modules associated with the pipelined processor include an instruction memory (IMEM) module adapted to share an IMEM output of the pipelined processor with each of the one or more further pipelined processors for use in the further multi-stage pipeline (Vorbach Figs 9 & 18, claim 3, [0390-0399], shared instruction memory IRAM, [0331], multistage pipeline).
Regarding claim 4, the combination of Vorbach and Goudie teaches the reconfigurable processor of claim 3, wherein the pipelined processor is further adapted to share the IF pipeline output of the IF stage as a further ID input to the further ID stage of each of the one or more further pipelined processors (Vorbach Fig 18, [0149], [0389-0390], [0459], sharing front-end pipeline stages and memory between cores & processing units).
Regarding claim 5, the combination of Vorbach and Goudie teaches the reconfigurable processor of claim 3, wherein the pipelined processor is further adapted to share the ID pipeline output of the ID stage as a further EX input to the further EX stage of each of the one or more further pipelined processors (Vorbach Fig 18, [0149], [0389-0390], [0459], sharing front-end pipeline stages and memory between cores & processing units).
Regarding claim 6, the combination of Vorbach and Goudie teaches the reconfigurable processor of claim 3, wherein the pipelined processor is further adapted to share the IF pipeline output of the IF stage as a further ID input to the further ID stage of each of the one or more further pipelined processors and to share the ID pipeline output of the ID stage as a further EX input to the further EX stage of each of the one or more further pipelined processors (Vorbach Fig 18, [0149], [0389-0390], [0459], sharing front-end pipeline stages and memory between cores & processing units, [0223-0225], [0337], registers for using and forwarding data).
Regarding claim 7, the combination of Vorbach and Goudie teaches the reconfigurable processor of claim 3, further comprising systolic registers adapted to transfer data between the pipelined processor and the one or more further pipelined processors (Vorbach [0223-0225], [0337], registers for using and forwarding data).
Regarding claim 8, the combination of Vorbach and Goudie teaches the reconfigurable processor of claim 3, further comprising an arithmetic logic unit (ALU) for each of the one or more further pipelined processors, the ALU being adapted to change a bit precision of a further EX stage output of the further EX stage (Vorbach [0947-0948], [1099], changing between 32-bit data-width and 4-bit blocks of data).
Regarding claim 9, the combination of Vorbach and Goudie teaches the reconfigurable processor of claim 8, wherein the ALU is adapted to change the bit precision from 4 bits to 32 bits and vice versa (Vorbach [0947-0948], [1099], changing between 32-bit data-width and 4-bit blocks of data).
Regarding claim 10, the combination of Vorbach and Goudie teaches the reconfigurable processor of claim 1, further comprising a watchdog unit adapted to monitor the pipelined processor for malfunctions or deadlock conditions ([0030], [0294-0297], watchdog and deadlock monitoring).
Claims 11-20 refer to a method embodiment of the processor embodiment of claims 1-10. Therefore, the above rejections for claims 1-10 are applicable to claims 11-20, respectively.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Cline (US 2024/0069921) discloses a reconfigurable processor for operating a multithreaded pipeline.
Mace (US 2019/0073225) discloses a reconfigurable processor with registers and other shared pipeline resources.
Leidel (US 2013/0332711) discloses a reconfigurable processor that interleaves threads during execution.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J METZGER whose telephone number is (571)272-3105. The examiner can normally be reached Monday-Friday 8:30-5.
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/MICHAEL J METZGER/ Primary Examiner, Art Unit 2183
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