DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1,2, 6, 9, and 14-22 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2, 6, and 8-13 of U.S. Patent No. 12,339,700. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the patent and the claims of the instant application commonly claim:
19/193,723
12,339,700
1. A circuit comprising:
a transmission line to propagate signal through a serially-arranged plurality of repeaters;
a control circuit to propagate control pulses to operate the repeaters in a current signaling mode (CMS);
the transmission line configured such that signals one the transmission line propagate in a voltage signaling mode (VMS) according to a first clock signal; and
a duration and timing of the CMS mode is determined by a second clock signal.
2. The circuit of claim 1, wherein a timing and duration of the control pulses is configured to
operate the repeaters in the CMS mode during a state transition of the signals at the repeaters
and to operate the repeaters in the VMS mode otherwise.
A circuit comprising:
a transmission line to propagate a signal through a serially-arranged plurality of repeaters;
a control circuit to propagate control pulses to the repeaters, wherein a timing and duration of the control pulses is configured to operate the repeaters in current-mode signaling (CMS) mode during a state transition of the signal at the repeaters and to operate the repeaters in voltage-mode signaling (VMS) mode otherwise; and the circuit configured such that propagation of the signal along the transmission line is initiated by a first clock signal and a duration and timing of the control pulses is determined by a second clock signal.
1. A circuit comprising: a transmission line to propagate a signal through a serially-arranged plurality of repeaters; a control circuit to propagate control pulses to the repeaters, wherein a timing and duration of the control pulses is configured to operate the repeaters in current-mode signaling (CMS) mode during a state transition of the signal at the repeaters and to operate the repeaters in voltage-mode signaling (VMS) mode otherwise;…
6. The circuit of claim 1, wherein the control circuit is configured to propagate the control pulses to the repeaters in VMS-mode.
2. The circuit of claim 1, wherein the control circuit is configured to propagate the control pulses to the repeaters in VMS-mode.
9. The circuit of claim 1, wherein the control pulses operate transmission gates shunting the repeaters.
6. The circuit of claim 1, wherein the control pulses operate transmission gates shunting the repeaters.
14. A circuit comprising:
a first clock pulse generator configured to generate a first clock pulse to a transmission
line;
a second clock pulse generator configured to generate a second clock pulse phase shifted
from the first clock pulse;
a control pulse generator configured to convert the second clock pulse into a control
pulse; and
a control circuit configured to propagate the control pulse sequentially to transmission
gates of the transmission line.
8. A circuit comprising:
a first clock pulse generator configured to generate a first clock pulse;
a second clock pulse generator configured to generate a second clock pulse earlier than the first clock pulse; a control pulse generator configured to convert the second clock pulse into a control pulse;
a transmission line configured to initiate propagation of a signal upon receiving the first clock pulse, the transmission line comprising a plurality of first repeaters, the first repeaters each shunted by a transmission gate; and
a control circuit configured to propagate the control pulse sequentially to the transmission gates.
15. The circuit of claim 14, wherein the control pulse generator comprises a configurable delay.
12. The circuit of claim 8, the control pulse generator comprising a third tunable delay element.
16. The circuit of claim 14, wherein the transmission line is configured to initiate propagation of a signal upon receiving the first clock pulse.
8. A circuit comprising: …a transmission line configured to initiate propagation of a signal upon receiving the first clock pulse,…
17. The circuit of claim 16, wherein the transmission line comprises a plurality of repeaters shunted by the transmission gates.
8. A circuit comprising:
… the transmission line comprising a plurality of first repeaters, the first repeaters each shunted by a transmission gate; …
18. The circuit of claim 14, wherein a timing and width of the control pulse are configured to close the transmission gates in advance of a state transition of the signal at inputs of the repeaters.
9. The circuit of claim 8, wherein a timing and width of the control pulse are configured to close the transmission gates in advance of a state transition of the signal at inputs of corresponding first repeaters of the transmission gates, and to open the transmission gates subsequent to the state transition of the signal at outputs of the corresponding first repeaters.
19. The circuit of claim 18, wherein the timing and width of the control pulse are further configured to open the transmission gates subsequent to the state transition of the signal at outputs of the repeaters.
9. The circuit of claim 8, wherein a timing and width of the control pulse are configured to…, and to open the transmission gates subsequent to the state transition of the signal at outputs of the corresponding first repeaters.
20. The circuit of claim 14, wherein the first clock pulse generator comprising a configurable delay.
10. The circuit of claim 8, the first clock pulse generator comprising a first tunable delay element.
21. The circuit of claim 14, wherein the second clock pulse generator comprises a configurable delay.
11. The circuit of claim 8, the second clock pulse generator comprising a second tunable delay element.
22. The circuit of claim 14, further comprising:
a plurality of stages;
a first configurable delay disposed between the first clock pulse generator and the
stages; and
a second configurable delay disposed between the second clock pulse generator and the stages.
13. The circuit of claim 8, further comprising:
a plurality of stages;
a fourth tunable delay element disposed between the first clock pulse generator and the stages; and
a fifth tunable delay element disposed between the second clock pulse generator and the stages.
Allowable Subject Matter
Claims 10-13 and 25 are allowed.
Claims 3-5, 7-8, and 23-24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Liang et al. (US 12,339,700) is the closest prior art of record and is the parent of the instant application.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CASSANDRA F COX whose telephone number is (571)272-1741. The examiner can normally be reached M-F 7:00-4:30; off alt Fridays.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CASSANDRA F COX/Primary Examiner, Art Unit 2836
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