Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Summary
2. Amendment of the patent application filed on June 11, 2026, has been received and made of record. In response to Non-Final Office Action mailed on March 12, 2026, applicant amended claims 1, 9-11, and 13-20 of which claims 1, 9, and 19 are independent claims. Claims 2-8, and 12 are maintained. NO claim has been cancelled and/or added as new claim after the Non-Final Office Action. Therefore, claims 1-20 are pending for consideration.
Response to Arguments
3. Applicant's arguments in “REMARKS” submitted on June 11, 2026, regarding independent claims 1, 9, and 19 have been fully considered but are moot in view of new ground of rejection as necessitated by the applicant’s amendment.
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
6. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
7. Claims 1-2, 4-10, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over SONG et al.(US 2023/0098891)(herein after SONG) in view of GAI et al.(US 2020/0335035 A1)(herein after GAI) .
Regarding claim 1, SONG teaches a pixel(fig.5, Para-96) comprising:
a light-emitting element(light-emitting element ED, fig.5, Para-99);
a first transistor(first transistor T1, fig. 5, Para-100) connected between a first power voltage(first driving voltage ELVDD, figs.3&5, Para-72) and the light-emitting element(ED), and configured to control a current(driving current Id) flowing through the light-emitting element(Para-104); and
a light-receiving element(light sensing element OPD, fig.5) connected between a fifth node(SN1, fig.5, Para-121) and a second power voltage(second driving voltage ELVSS, fig.5, Para-121),
Nevertheless, SONG is not found to teach expressly the pixel circuit, wherein a voltage of the fifth node corresponds to a light amount applied to the light-receiving element, and wherein a sensing current transmitted to a readout line by passing through the first transistor corresponds to the voltage of the fifth node.
However, GAI teaches a pixel circuit, wherein a voltage of the fifth node(third node N3, figs.3, 8B, Para-63) corresponds to a light amount applied to the light-receiving element(Para 83-85), and
wherein a sensing current transmitted to a readout line by passing through the first transistor corresponds to the voltage of the fifth node(N3, figs.7&8B, Para 83-85).
The prior art, as embodied in the teachings of SONG and GAI, included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. One of ordinary skill in the art could have combined the elements as claimed by known methods and in that combination each element merely performs the same function as it does separately. Such combination is reasonable as it provides a pixel circuit of a display device than could compensate for brightness uniformity.
Regarding claim 2, SONG as modified by GAI teaches the pixel according to claim 1, wherein the first transistor(T1, fig.5, SONG) comprises a control electrode(gate of T1) connected to a first node(N1), a first electrode(drain or source of T1) connected to a fourth node(node between source of ET1 and drain of T1), and a second electrode(source or drain of T1, fig.5) connected to a second node(node between source of T1 and drain of ET2, fig.5, SONG), and
wherein the pixel(PXij) further comprises:
a ninth transistor(T1, fig.8B, GAI) connected between the second node(N2) and the fifth node(N3, fig.8B, GAI); and
a tenth transistor(ST1, fig.5, SONG; T2, fig.8B, GAI) connected between a reset voltage(RST, fig.5, SONG; S2, fig.8B, GAI) and the fifth node(SN1, fig.5, SONG; N3, fig.8B, GAI).
Regarding claim 4, SONG as modified by GAI teaches the pixel according to claim 2, further comprising a second transistor (second transistor T2, fig.5, SONG) connected between the fourth node(node between ET1 and T1) and a data line(Di, fig.5, SONG)(for motivation, see the rejection of claim 2).
Regarding claim 5, SONG as modified by GAI teaches the pixel according to claim 2, further comprising a storage capacitor (Cst, fig.5, SONG) connected between the first power voltage (ELVDD, fig.5, SONG) and the first node(N1, fig.5, SONG).
Regarding claim 6, SONG as modified by GAI teaches the pixel according to claim 2, further comprising a third transistor (T3) connected between the first node(N1, fig.5, SONG) and the second node(node between T1 and ET2, fig.5, SONG).
Regarding claim 7, SONG as modified by GAI teaches the pixel according to claim 2, wherein the light-emitting element(ED, fig.5, SONG) comprises an anode electrode(fig.5) connected to a third node(node between ET2 and ED, fig.5, SONG), and
a cathode electrode(fig.5) connected to the second power voltage(ELVSS, fig.5, SONG), and
wherein the pixel(PXij, fig.5, SONG) further comprises:
a fifth transistor(ET1, fig.5, SONG) connected between the first power voltage(ELVDD) and the fourth node(node between ET1 and T1, fig.5, SONG); and
a sixth transistor(ET2, fig.5, SONG) connected between the second node(node between T1 and ET2, fig.5, SONG) and the third node(node between ET2 and ED, fig.5, SONG).
Regarding claim 8, SONG as modified by GAI teaches the pixel according to claim 7, further comprising:
a fourth transistor(T4, fig.5, SONG) connected between the first node(N1) and a first initialization voltage(VINT1, fig.5, Para-107, SONG); and
a seventh transistor(T5, fig.5, SONG) connected between the third node(node between ET2 and anode of ED, fig.5, SONG) and a second initialization voltage(VINT2, fig.5, Para-111, SONG).
Claim 9 is rejected for the same reason as mentioned in the rejection of claim 1, since both claims 1 and 9 recite identical claim limitations except minor change in preamble. The additional claim limitations, “a display panel comprising pixels; and a display panel driver configured to drive the display panel” are also disclosed by SONG in fig.3 and Para-68, 71 and 74.
Claim 10 is rejected for the same reason as mentioned in the rejection of claim 2, since both claims 2 and 10 recite identical claim limitations except minor change in preamble.
Claim 19 is rejected for the same reason as mentioned in the rejection of claim 9, since both claims 9 and 19 recite identical claim limitations except minor change in preamble. The additional claim limitations, “a processor configured to provide input image data to a display device that is configured to display an image based on the input image data; and a power supply(voltage generator 400, fig.3, Para-72, SONG) configured to supply power(ELVDD, ELVSS, VINT1/VINT2) to the display device” are also disclosed by SONG in fig.1, and Para 70-72 and 74).
Claim 20 is rejected for the same reason as mentioned in the rejection of claim 2, since both claims 2 and 20 recite identical claim limitations except minor change in preamble.
8. Claims 3, 11, and 13-17 are rejected under 35 U.S.C. 103 as being unpatentable over SONG et al.(US 2023/0098891) in view of GAI et al.(US 2020/0335035 A1)and further in view of Choi et al.(US 2022/0012453) (herein after Choi).
Regarding claim 3, SONG as modified by GAI is not found to teach expressly the pixel according to claim 2, further comprising an eighth transistor connected between the fourth node and the readout line.
However, Choi teaches pixel circuit in a light emitting display device, further comprising: an eighth transistor(M10, fig.2, Para-46) connected between the fourth node(221, fig.2) and the readout line(OUT, fig.2, Para-46-48).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filling date of the application, to have modified SONG further with the teaching of Choi to include the feature in order to provide a pixel circuit that prevents a decrease in luminance of self-luminous element over time and extends the life of the self-luminous element.
Claim 11 is rejected for the same reason as mentioned in the rejection of claim 3, since both claims 3 and 11 recite identical claim limitations except minor change in preamble.
Claim 13 is rejected for the same reason as mentioned in the rejection of claim 4, since both claims 4 and 13 recite identical claim limitations except dependency of the respective claims.
Claim 14 is rejected for the same reason as mentioned in the rejection of claim 5, since both claims 5 and 14 recite identical claim limitations except dependency of the respective claims.
Claim 15 is rejected for the same reason as mentioned in the rejection of claim 6, since both claims 6 and 15 recite identical claim limitations except dependency of the respective claims.
Claim 16 is rejected for the same reason as mentioned in the rejection of claim 7, since both claims 7 and 16 recite identical claim limitations except dependency of the respective claims.
Claim 17 is rejected for the same reason as mentioned in the rejection of claim 8, since both claims 8 and 17 recite identical claim limitations except dependency of the respective claims.
9. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over SONG et al.(US 2023/0098891 A1), GAI et al.(US 2020/0335035 A1), Choi et al.(US 2022/0012453 A1) and further in view of Liu et al.(US 2019/0164493 A1) (herein after Liu).
Regarding claim 12, SONG as modified by GAI and Choi is not found to teach expressly the display device according to claim 11, further comprising: switches configured to selectively connect a transmission/reception line corresponding to one or more of the pixels to one of a bias voltage line or a readout line corresponding to the one or more pixels; and a readout circuit connected to the readout line.
However, Liu teaches a pixel unit circuit of a display device, comprising:
switches(multiplexer sub-circuit MUX, fig.4, Para-126) configured to selectively connect a transmission/reception line corresponding to one or more of the pixels to one of a bias voltage line or a readout line(reading line RL, fig.4, Para-126) corresponding to the one or more pixels(fig.4); and a readout circuit(control circuit 40, fig.4, Para-126) connected to the readout line(RL).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filling date of the claimed invention, to have modified SONG further with the teaching of Liu to include the feature in order to provide pixel circuit in display device that ensures high pixel per inch(PPI) of a product.
Allowable Subject Matter
10. Claim 18 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
11. The following is a statement of reasons for the indication of allowable subject matter:
Claim 18: None of the cited prior arts, on record, taken alone in combination, provides a motivation to fairly teach or suggest the applicant’s claimed invention, “the display device according to claim 17, wherein the one of the pixels further comprises a second transistor connected between the fourth node and a data line, wherein one of the pixels further comprises a third transistor connected between the first node and the second node, wherein the first(T1), second(T2), fifth(T5), sixth(T6), seventh(T7), eighth(T8), and ninth transistors(T9, fig.4) comprise PMOS transistors, and wherein the third(T3), fourth(T4), and tenth transistors(T10, fig.10) comprise NMOS transistors”.
Conclusion
12. Applicant's amendment necessitated the new ground of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Examiner Note
13. The Examiner cites particular figures, paragraphs, columns and line numbers in the reference(s), as applied to the claims above. Although the particular citations are representative teachings and are applied to specific limitations within the claims, other passages, internally cited references, and figures may also apply. In preparing a response, it is respectfully requested that the Applicant fully consider the references, in their entirety, as potentially disclosing or teaching all or part of the claimed invention, as well as fully consider the context of the passage as taught by the reference(s) or as disclosed by the Examiner.
Contact
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MD SAIFUL A SIDDIQUI whose telephone number is (571)270-1530. The examiner can normally be reached Mon-Fri: 9:00AM - 5:30PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Temesghen Ghebretinsae, can be reached at (571) 272-3017. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MD SAIFUL A SIDDIQUI/
Primary Examiner, Art Unit 2626
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