DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
SUMMARY
2. The patent application submitted on April 30, 2025, has been received and recorded. There are 1-20 claims in the application of which claims 1, 9, and 19 are independent claims. Therefore, claims 1-20 are pending for consideration.
Information Disclosure Statement
3. The information disclosure statement(IDS) submitted was filed along with the mailing date of the patent application on April 30, 2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
7. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
8. Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over WANG et al.(US 2019/0279566 A1)(herein after WANG).
Regarding claim 1, WANG teaches a pixel(pixel circuit, a display panel, Para-2) comprising:
a light-emitting element(EL, light-emitting element 110, figs.2a-2b, Para-38);
a first transistor(third transistor M3, figs.2b-2c, 4a, Para-68) connected between a first power voltage(first power supply terminal V1, fig.4a, Para-68) and the light-emitting element (EL), and configured to control a current(magnitude of light emitting current) flowing through the light-emitting element (Para-71); and
a light-receiving element(photodiode PD, figs.2a-2c, 3a) connected between a fifth node(third end a3, fig.2c, Para-44) and a second power voltage(biased voltage terminal VBIAS, fig.2c, Para-49),
wherein a voltage of the fifth node(third end a3) corresponds to a light amount applied to the light-receiving element (PD)(Para-44), and
wherein a current transmitted to a readout line through the first transistor corresponds to the voltage of the fifth node (Para-44: the third end a3 of the light-emitting control circuit 120 can input a constant and controllable predetermined current to the sense signal output end b1 of the photoelectric sense circuit 130, so that the sense electrical signal of the photoelectric sense circuit 130 can be output to the sense signal output end b1 of the photoelectric sense circuit 130).
9. Claims 2, 4-10, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over WANG et al.(US 2019/0279566 A1) in view of SONG et al.(US 2023/0098891)(herein after SONG).
Regarding claim 2, WANG teaches the pixel according to claim 1, wherein the first transistor(M3, fig.2c) comprises a control electrode(gate of M3), a first electrode(drain or source of M3), and a second electrode(source or drain of M3, fig.2c), and
wherein the pixel(100) further comprises:
a ninth transistor(M7, fig.2c) connected between the second node(node between M3 and M6) and the fifth node(a3); and
a tenth transistor(M8) connected between a reset voltage(V2) and the fifth node(a3, fig.2c)(Para-50).
Nevertheless, WANG is not found to teach expressly the pixel, wherein the first transistor comprises a control electrode connected to a first node, a first electrode connected to a fourth node, and a second electrode connected to a second node.
However, SONG teaches a pixel(PXij) and optical sensor circuit (FXij)(fig.5, Para-96) wherein the first transistor(first transistor T1, fig.5, Para-100) comprises a control electrode connected to a first node(first node N1, fig.5, Para-106), a first electrode connected to a fourth node(node between ET1 and T1), and a second electrode connected to a second node(node between T1 and ET2), and
wherein the pixel further comprises:
a tenth transistor(ST1, fig.5, Para-122) connected between a reset voltage(reset signal RST, fig.5, Para-127) and the fifth node(first sensing node SN1, fig.5, Para-121).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filling date of the application, to have modified WANG with the teaching of SONG to include the feature in order to provide a display device capable of recognizing improved biometric information efficiently.
Regarding claim 4, WANG as modified by SONG teaches the pixel according to claim 2, further comprising a second transistor (second transistor T2, fig.5, SONG) connected between the fourth node(node between ET1 and T1) and a data line(Di, fig.5, SONG)(for motivation, see the rejection of claim 2).
Regarding claim 5, WANG as modified by SONG teaches the pixel according to claim 2, further comprising a storage capacitor (Cst, fig.5, SONG; C1, fig.2c, WANG) connected between the first power voltage(V1, fig.2c, WANG; ELVDD, fig.5, SONG) and the first node(N2, fig.2c, WANG; N1, fig.5, SONG) (for motivation, see the rejection of claim 2).
Regarding claim 6, WANG as modified by SONG teaches the pixel according to claim 2, further comprising a third transistor (T3) connected between the first node(N1, fig.5, SONG) and the second node(node between T1 and ET2, fig.5, SONG) (for motivation, see the rejection of claim 2).
Regarding claim 7, WANG as modified by SONG teaches the pixel according to claim 2, wherein the light-emitting element(EL, fig.2c, WANG) comprises an anode electrode(c1) connected to a third node(second end a2, fig.2c, Para-40, WANG), and
a cathode electrode(c2) connected to the second power voltage(second power supply terminal V2, fig.2b, fig.2b, Para-40, WANG), and
wherein the pixel(100, fig.2b, WANG) further comprises:
a fifth transistor(ET1, fig.5, SONG) connected between the first power voltage(ELVDD) and the fourth node(node between ET1 and T1, fig.5, SONG) (for motivation, see the rejection of claim 2); and
a sixth transistor(M6, fig.2b, WANG) connected between the second node(node between M3 and M6) and the third node(second end a2, fig.2c, Para-40, WANG).
Regarding claim 8, WANG as modified by SONG teaches the pixel according to claim 7, further comprising:
a fourth transistor(T4, fig.5, SONG) connected between the first node(N1) and a first initialization voltage(VINT1, fig.5, Para-107, SONG); and
a seventh transistor(T5, fig.5, SONG) connected between the third node(node between ET2 and anode of ED, fig.5, SONG) and a second initialization voltage(VINT2, fig.5, Para-111, SONG)(for motivation, see the rejection of claim 2).
Claim 9 is rejected for the same reason as mentioned in the rejection of claim 1, since both claims 1 and 9 recite identical claim limitations except minor change in preamble. The additional claim limitations, “a display panel comprising pixels; and a display panel driver configured to drive the display panel” are also disclosed by SONG in fig.3 and Para-68, 71 and 74(for motivation, see the rejection of claim 2).
Claim 10 is rejected for the same reason as mentioned in the rejection of claim 2, since both claims 2 and 10 recite identical claim limitations except minor change in preamble.
Claim 19 is rejected for the same reason as mentioned in the rejection of claim 9, since both claims 9 and 19 recite identical claim limitations except minor change in preamble. The additional claim limitations, “a processor configured to provide input image data to a display device that is configured to display an image based on the input image data; and a power supply(voltage generator 400, fig.3, Para-72, SONG) configured to supply power(ELVDD, ELVSS, VINT1/VINT2) to the display device” are also disclosed by SONG in fig.1, and Para 70-72 and 74)(for motivation, see the rejection of claim 2).
Claim 20 is rejected for the same reason as mentioned in the rejection of claim 2, since both claims 2 and 20 recite identical claim limitations except minor change in preamble.
10. Claims 3, 11, and 13-17 are rejected under 35 U.S.C. 103 as being unpatentable over WANG et al.(US 2019/0279566 A1) in view of SONG et al.(US 2023/0098891) and further in view of Choi et al.(US 2022/0012453) (herein after Choi).
Regarding claim 3, WANG as modified by SONG is not found to teach expressly the pixel according to claim 2, further comprising an eighth transistor connected between the fourth node and the readout line.
However, Choi teaches pixel circuit in a light emitting display device, further comprising:
an eighth transistor(M10, fig.2, Para-46) connected between the fourth node(221, fig.2) and the readout line(OUT, fig.2, Para-46-48).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filling date of the application, to have modified WANG further with the teaching of Choi to include the feature in order to provide a pixel circuit that prevents a decrease in luminance of self-luminous element over time and extends the life of the self-luminous element.
Claim 11 is rejected for the same reason as mentioned in the rejection of claim 3, since both claims 3 and 11 recite identical claim limitations except minor change in preamble.
Claim 13 is rejected for the same reason as mentioned in the rejection of claim 4, since both claims 4 and 13 recite identical claim limitations except dependency of the respective claims.
Claim 14 is rejected for the same reason as mentioned in the rejection of claim 5, since both claims 5 and 14 recite identical claim limitations except dependency of the respective claims.
Claim 15 is rejected for the same reason as mentioned in the rejection of claim 6, since both claims 6 and 15 recite identical claim limitations except dependency of the respective claims.
Claim 16 is rejected for the same reason as mentioned in the rejection of claim 7, since both claims 7 and 16 recite identical claim limitations except dependency of the respective claims.
Claim 17 is rejected for the same reason as mentioned in the rejection of claim 8, since both claims 8 and 17 recite identical claim limitations except dependency of the respective claims.
11. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over WANG et al.(US 2019/0279566 A1), SONG et al.(US 2023/0098891 A1), Choi et al.(US 2022/0012453 A1) and further in view of Liu et al.(US 2019/0164493 A1) (herein after Liu).
Regarding claim 12, WANG as modified by SONG and Choi is not found to teach expressly the display device according to claim 11, further comprising: switches configured to selectively connect a transmission/reception line corresponding to one or more of the pixels to one of a bias voltage line or a readout line corresponding to the one or more pixels; and a readout circuit connected to the readout line.
However, Liu teaches a pixel unit circuit of a display device, comprising:
switches(multiplexer sub-circuit MUX, fig.4, Para-126) configured to selectively connect a transmission/reception line corresponding to one or more of the pixels to one of a bias voltage line or a readout line(reading line RL, fig.4, Para-126) corresponding to the one or more pixels(fig.4); and a readout circuit(control circuit 40, fig.4, Para-126) connected to the readout line(RL).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filling date of the claimed invention, to have modified WANG further with the teaching of Liu to include the feature in order to provide pixel circuit in display device that ensures high pixel per inch(PPI) of a product.
Allowable Subject Matter
12. Claim 18 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
13. The following is a statement of reasons for the indication of allowable subject matter:
Claim 18: None of the cited prior arts, on record, taken alone in combination, provides a motivation to fairly teach or suggest the applicant’s claimed invention, “the display device according to claim 17, wherein the pixels further comprise a second transistor connected between the fourth node and a data line, wherein the pixels further comprise a third transistor connected between the first node and the second node, wherein the first(T1), second(T2), fifth(T5), sixth(T6), seventh(T7), eighth(T8), and ninth transistors(T9, fig.4) comprise PMOS transistors, and wherein the third(T3), fourth(T4), and tenth transistors(T10, fig.10) comprise NMOS transistors”.
Examiner Note
14. The Examiner cites particular figures, paragraphs, columns and line numbers in the references, as applied to the claims above. Although the particular citations are representative teachings and are applied to specific limitations within the claims, other passages, internally cited references, and figures may also apply. In preparing a response, it is respectfully requested that the Applicant fully consider the references, in their entirety, as potentially disclosing or teaching all or part of the claimed invention, as well as fully consider the context of the passage as taught by the references or as disclosed by the Examiner.
Contact
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MD SAIFUL A SIDDIQUI whose telephone number is (571)270-1530. The examiner can normally be reached Mon-Fri: 9:00AM - 5:30PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Temesghen Ghebretinsae, can be reached on (571) 272-3017. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MD SAIFUL A SIDDIQUI/Primary Examiner, Art Unit 2626