DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4-13, 15, and 16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Morii (US PGPUB 2020/0212892).
Regarding claim 1, Figure 2 of Morii discloses an apparatus, comprising:
a first transistor with a first terminal, a first gate, and a second terminal [QH]
a second transistor with a third terminal, a second gate, and a fourth terminal [QL]
wherein the second terminal of the first transistor is electrically coupled to the fourth terminal of the second transistor by an electrically conductive path [R and SC]
wherein the third terminal is grounded [V-]
a power supply electrically coupled to the first terminal of the first transistor [V+]
a capacitor electrically coupled to the electrically conductive path [SC]
a power source electrically coupled to the electrically conductive path [F]
Regarding claim 4, Figure 2 of Morii discloses wherein the first transistor and/or the second transistor comprise a metal-oxide-semiconductor field-effect transistor (MOSFET) [QH and QL].
Regarding claim 5, Figure 2 of Morii discloses an RF choke along the electrically conductive path between the first transistor and the second transistor [FL].
Regarding claim 6, Figure 2 of Morii discloses wherein the first gate and the second gate are electrically coupled to a half-bridge driver [4].
Regarding claim 7, Figure 2 of Morii discloses wherein the capacitor is electrically coupled to an RF trace [101].
Regarding claim 8, Figure 2 of Morii discloses wherein the power supply is a DC power supply [V+].
Regarding claim 9, Figure 2 of Morii discloses wherein the power source is electrically floating with respect to the electrically conductive path [Figure 2].
Regarding claim 10, Figure 2 of Morii discloses wherein the first transistor and the second transistor are configured to be driven to opposite states during operation of the apparatus [QH and QL].
Regarding claim 11, Figure 2 of Morii discloses an apparatus, comprising:
a capacitor with a first terminal and a second terminal [SC]
a pullup transistor electrically coupled to the first terminal [QH]
a pulldown transistor electrically coupled to the first terminal [QL]
a half-bridge driver configured to control the pullup transistor and the pulldown transistor [4]
Regarding claim 12, Figure 2 of Morii discloses wherein the pulldown transistor is electrically coupled to ground, and wherein the pullup transistor is electrically coupled to a power supply [V+ and V-].
Regarding claim 13, Figure 2 of Morii discloses an RF choke electrically coupled between the pullup transistor and the pulldown transistor [FL].
Regarding claim 15, Figure 2 of Morii discloses wherein the second terminal of the capacitor is electrically coupled to an RF trace [101].
Regarding claim 16, Figure 2 of Morii discloses wherein the pullup transistor and the pulldown transistor are configured to be in different states during operation of the apparatus [QH and QL].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 3, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Morii (US PGPUB 2020/0212892).
Regarding claim 2, Morii does not explicitly disclose wherein the first transistor and/or the second transistor comprise a silicon carbide semiconductor material.
However, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Figure 2 of Morii by using silicon carbide transistors as a matter of simple design-choice, since it was well-known in the art to use silicon carbide transistors in driver circuits.
Regarding claim 3, Morii does not explicitly disclose wherein the first transistor and/or the second transistor comprise a gallium nitride semiconductor material.
However, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Figure 2 of Morii by using gallium nitride transistors as a matter of simple design-choice, since it was well-known in the art to use gallium nitride transistors in driver circuits.
Regarding claim 14, Morii does not explicitly disclose wherein the pullup transistor and/or the pulldown transistor comprise semiconductor materials with bandgaps that are 1.5eV or higher.
However, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Figure 2 of Morii by using bandgaps that are 1.5eV or higher as a matter of simple design-choice, since it has been held that where the general conditions of a claim are met in the prior art, discovering the optimum or workable ranges involves only routine skill in the art.
Claim(s) 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mavretic (US PGPUB 2019/0267212).
Regarding claim 17, Figure 2 of Mavretic discloses an apparatus, comprising:
a board [235; inherent]
an electrically conductive trace on the board [232]
a plurality of switched shunt capacitors that are each electrically coupled to the board [C11, C12, and C1N]
wherein each of the plurality of switched shunt capacitors are configured to be charged and discharged by a corresponding circuit that comprises a transistor with a semiconductor material with a bandgap [S11, S12, S1N, and 242].
Mavretic does not explicitly disclose a semiconductor material with a bandgap that is 1.5eV or higher.
However, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Figure 2 of Mavretic by using bandgaps that are 1.5eV or higher as a matter of simple design-choice, since it has been held that where the general conditions of a claim are met in the prior art, discovering the optimum or workable ranges involves only routine skill in the art.
Regarding claim 18, Mavretic, as applied to claim 17, does not explicitly disclose wherein the plurality of switched shunt capacitors comprises a plurality of different capacitance values.
However, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Figure 2 of Mavretic, as applied to claim 17, by using different capacitor values as a matter of simple design-choice, since it was well-known in the art to use different values of capacitors in a variable capacitor circuit.
Regarding claim 19, Mavretic, as applied to claim 17, does not explicitly disclose wherein each of the plurality of switched shunt capacitors are controlled by a pair of transistors arranged in a half-bridge configuration.
However, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Figure 2 of Mavretic, as applied to claim 17, by using a half-bridge driver to drive the switches as a matter of simple design-choice, since it was well-known in the art to use half-bridge drivers as switch drivers.
Regarding claim 20, Figure 2 of Mavretic, as applied to claim 17, discloses wherein each of the plurality of switched shunt capacitors comprises a switch along an electrical path between a power source and a capacitor [S11, S12, S1N, and 242].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Tomi S Skibinski whose telephone number is (571)270-7581. The examiner can normally be reached Mon. - Thurs. 8am - 6pm.
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/TOMI SKIBINSKI/Primary Examiner, Art Unit 2836
