DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
In addressing the rejection ground, each claim may not have been separately discussed to the extent the claimed features are the same as or similar to the previously-discussed features; the previous discussion is construed to apply for the other claims in the same or similar way.
In the office action, “/” should be read as and/or as generally understood. For example, “A/B” means A and B, or A or B.
Claim Objections
Claims 6-7 and 15-16 are objected to because of the following informalities:
Claim 6 recites “the first end of the first comparison unit”. It should be recited as --the first input end of the first comparison unit--.
Claim 7 is objected to based on the dependency from claim 6.
Analogously, claim 15 has the same issue as discussed in claim 6.
Claim 16 is objected to based on the dependency from claim 15.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 6-7, 9 and 15-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al. (US 11,368,145).
Regarding claim 1, Liu discloses a digital display control buffer circuit [e.g. fig. 3/5], the digital display control buffer circuit at least comprising a glitch removal circuit [e.g. 548, MP5, MP6, MN2], a first comparison unit [e.g. 532/536], a second comparison unit [e.g. 536/532] and a first switch device [e.g. MP7]; a first end of the first switch device and a first input end of the second comparison unit are used to input an upstream signal [e.g. the supply voltage] of the digital display control buffer circuit, a first input end [e.g. the lower terminal] of the first comparison unit is used to input a downstream signal [see ground] of the digital display control buffer circuit; a first input end [e.g. the gate of MP5/MP6] of the glitch removal circuit is electrically connected to an output end of the first comparison unit, a second input end [e.g. the gate of MP6/MP5] of the glitch removal circuit is electrically connected to an output end of the second comparison unit, and an output end of [e.g. the output terminal of 542] the glitch removal circuit is electrically connected to a control end of the first switch device, and the glitch removal circuit is used to output a control signal to the control end of the first switch device when a first signal outputted by the output end of the second comparison unit is a falling edge [e.g. the second comparator is at falling edge and the first comparison unit maintains low], such that the first switch device is turned off.
Regarding claim 6, Liu discloses the digital display control buffer circuit according to claim 1, wherein the digital display control buffer circuit further comprises: a second switch device [e.g. MN1], wherein a control end of the second switch device is electrically connected to the output end of the second comparison unit, a first end of the second switch device is electrically connected to the first end of the first comparison unit [e.g. 538], and a second end of the second switch device is grounded.
Regarding claim 7, Liu discloses the digital display control buffer circuit according to claim 6, wherein the second switch device is a second NMOS transistor, a gate of the second NMOS transistor is the control end of the second switch device, a drain of the second NMOS transistor is the first end of the second switch device [e.g. ground signal flows via MN2 to MN1] , and a source of the second NMOS transistor is the second end of the second switch device.
Regarding claim 9, Liu discloses a digital display control buffer apparatus, comprising a digital display control buffer circuit [see at least Col. 4, lines 5-54], the digital display control buffer circuit at least comprising a glitch removal circuit, a first comparison unit, a second comparison unit and a first switch device; a first end of the first switch device and a first input end of the second comparison unit are used to input an upstream signal of the digital display control buffer circuit, a first input end of the first comparison unit is used to input a downstream signal of the digital display control buffer circuit; a first input end of the glitch removal circuit is electrically connected to an output end of the first comparison unit, a second input end of the glitch removal circuit is electrically connected to an output end of the second comparison unit, and an output end of the glitch removal circuit is electrically connected to a control end of the first switch device, and the glitch removal circuit is used to output a control signal to the control end of the first switch device when a first signal outputted by the output end of the second comparison unit is a falling edge, such that the first switch device is turned off. Please see rejection of claim 1.
Regarding claim 15, Liu discloses the digital display control buffer apparatus according to claim 9, wherein the digital display control buffer circuit further comprises: a second switch device, wherein a control end of the second switch device is electrically connected to the output end of the second comparison unit, a first end of the second switch device is electrically connected to the first end of the first comparison unit, and a second end of the second switch device is grounded. Please see rejection of claim 6.
Regarding claim 16, Liu discloses the digital display control buffer apparatus according to claim 15, wherein the second switch device is a second NMOS transistor, a gate of the second NMOS transistor is the control end of the second switch device, a drain of the second NMOS transistor is the first end of the second switch device, and a source of the second NMOS transistor is the second end of the second switch device. Please see rejection of claim 7.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Almazon et al. (US 2016/0164506).
Regarding claim 1, Almazon discloses a digital display control buffer circuit [e.g. fig. 6/9], the digital display control buffer circuit at least comprising a glitch removal circuit [e.g. 210/226], a first comparison unit [e.g. 206], a second comparison unit [e.g. 208] and a first switch device [e.g. 216/218]; a first end of the first switch device and a first input end of the second comparison unit are used to input an upstream signal [e.g. the supply voltage] of the digital display control buffer circuit, a first input end [e.g. the lower terminal] of the first comparison unit is used to input a downstream signal [see 222/ground] of the digital display control buffer circuit; a first input end [e.g. the upper terminal of 210] of the glitch removal circuit [e.g. 210, 212/226/582/584] is electrically connected to an output end of the first comparison unit, a second input end [e.g. the lower terminal of 212] of the glitch removal circuit is electrically connected to an output end of the second comparison unit, and an output end of [e.g. the output terminal of 210] the glitch removal circuit is electrically connected to a control end of the first switch device, and the glitch removal circuit is used to output a control signal to the control end of the first switch device when a first signal outputted by the output end of the second comparison unit is a falling edge [see at least fig. 5], such that the first switch device is turned off.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Almazon et al. (US 2016/0164506) in view of Sansom et al. (US 2019/0260770).
Regarding claim 9, Almazon discloses a digital display control buffer apparatus, comprising a digital display control buffer circuit, the digital display control buffer circuit at least comprising a glitch removal circuit, a first comparison unit, a second comparison unit and a first switch device; a first end of the first switch device and a first input end of the second comparison unit are used to input an upstream signal of the digital display control buffer circuit, a first input end of the first comparison unit is used to input a downstream signal of the digital display control buffer circuit; a first input end of the glitch removal circuit is electrically connected to an output end of the first comparison unit, a second input end of the glitch removal circuit is electrically connected to an output end of the second comparison unit, and an output end of the glitch removal circuit is electrically connected to a control end of the first switch device, and the glitch removal circuit is used to output a control signal to the control end of the first switch device when a first signal outputted by the output end of the second comparison unit is a falling edge, such that the first switch device is turned off. Please see rejection of claim 1.
Almazon does not explicitly disclose a digital display. However, it’s well-known to utilize a digital display to provide alert or parameters. For example, Sansom discloses to utilize a digital display to provide alert or parameters [see at least para. 0023, fig. 2].
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Almazon in accordance with the teaching of Sansom regarding a digital display in order to provide these metrics and alerts to the display module for visualization on the user interface [para. 0023].
Allowable Subject Matter
Claims 2-5, 8, 10-14 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PATRICK C CHEN whose telephone number is (571)270-7207. The examiner can normally be reached M-F Flexible 8:00-16:30.
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/PATRICK C CHEN/Primary Examiner, Art Unit 2836
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