DETAILED ACTIONNotice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 9-11, 19 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KIM et al (2023/0057700) (herein “KIM”). In regards to claim 1, 11 and 20, KIM teaches a display device comprising: a display panel comprising a pixel configured to receive a driving voltage through a driving voltage line (See; Figs. 1-3 for display panel 110 having subpixels SP and driving voltage line DVL); a panel driver configured to drive the display panel (See; Figs. 1 and 2); a voltage generator configured to generate the driving voltage, and determine a voltage level of the driving voltage based on a voltage control signal (See; Fig. 1 for power management circuit 150 supplying a driving voltage); a driving controller configured to control a driving of the panel driver, and supply the voltage control signal to the voltage generator (See; Fig. 1 for timing controller 140); and a voltage detector between the voltage generator and the driving voltage line, and configured to sense a sensing voltage corresponding to a current flowing into the driving voltage line, and output a sensing signal based on the sensing voltage (See; Fig. 5 and p[0113]-p[0116] for current detecting circuit 310 having resistor 312 for sensing a current and outputting a signal based on the sensed value), wherein the driving controller is configured to: receive the sensing signal from the voltage detector; and generate the voltage control signal based on the sensing signal (See; Fig. 5 and p[0114]-p[0118] where timing controller 140 receives the sensed value from the current detecting circuit 310 and generates a control signal BDP based on the sensing signal). Claim 11 is a broader recitation of claim 1, however the rejection above covers all aspects of claim 11. Claim 20 reads on everything in the rejection of claim 1, including a main processor configured to provide an image signal to the driving controller (See; Fig. 1 for host system 200). In regards to claim 9, KIM teaches wherein the driving voltage line comprises a first driving voltage line and a second driving voltage line, and wherein the pixel comprises: a driving transistor connected to the first driving voltage line configured to receive a first driving voltage (See; Fig. 5 for DRT connected to DVL / EVDD); and a light emitting element connected between the driving transistor and the second driving voltage line configured to receive a second driving voltage (See; Fig. 5 for ED connected to EVSS).
In regards to claim 10, KIM teaches wherein the voltage detector is connected between the voltage generator and the second driving voltage line as the driving voltage line (See; Fig. 5 for detector 310). In regards to claim 19, KIM teaches wherein the driving voltage line comprises a first driving voltage line and a second driving voltage line, and wherein the pixel comprises: a driving transistor connected to the first driving voltage line configured to receive a first driving voltage (See; Fig. 5 for DRT connected to DVL / EVDD); and a light emitting element connected between the driving transistor and the second driving voltage line configured to receive a second driving voltage (See; Fig. 5 for ED connected to EVSS), wherein the driving voltage is one of the first driving voltage or the second driving voltage, and wherein the voltage controller is connected between the voltage generator and the second driving voltage line (See; Figs. 1 and 5).
Allowable Subject Matter
Claims 2-8 and 12-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN A BOYD whose telephone number is (571)270-7503. The examiner can normally be reached Mon - Fri 8:00 - 5:00.
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/JONATHAN A BOYD/Primary Examiner, Art Unit 2627
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