DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 and 20 are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Kim et al (US 2023/0189567; provided by Applicant).
In regards to claims 1 and 20, Kim discloses an electronic device (paragraph 50; products):
a housing (it is inherent that the products which have the display panel would have a housing);
a display device (display device 1) which is accommodated in the housing and displays an image (Fig. 1 and paragraph 50), the display device including:
a light-emitting element (OLED) (Fig. 4 and paragraph 69);
a first transistor (transistor T1) which generates a driving current applied to the light-emitting element (Fig, 4 and paragraphs 71, 75-77), the first transistor including:
a first channel area (Fig. 5 and paragraphs 137-138; CH1 of ACT1);
a second transistor (transistor T2) which applies a data voltage to the first transistor in response to a first gate signal (Fig. 4 and paragraphs 72 78), the second transistor including:
a second channel area (CH2 of ACT2) disposed in a different layer from the first channel area (Fig. 5 and paragraphs 112-113);
a third transistor (transistor T5) which applies a power voltage to the first transistor in response to a second gate signal (Fig. 4 and paragraphs 72, 82), the third transistor including:
a third channel area (CH5 of ACT5) disposed in a different layer from each of the first channel area and the second channel area (Fig. 5 and paragraphs 164-165); and
a fourth transistor (transistor T6) which electrically connects the first transistor and the light-emitting element in response to a light-emitting signal (Fig. 4 and paragraphs 72, 75, 83), the fourth transistor including:
a fourth channel area (CH6 of ACT6) disposed in a different layer from each of the first channel area and the second channel area (Fig. 5 and paragraphs 164-165).
In regards to claim 2, Kim discloses the display device of claim 1, wherein the first channel area (CH1 of ACT1) is disposed in a first semiconductor layer (SC2) (Fig. 5 and paragraphs 137-138), and
the second channel area (CH2 of ACT2) is disposed in a second semiconductor layer (SC1) on which the first semiconductor layer is disposed (Fig. 5 and paragraphs 112-113).
In regards to claim 3, Kim discloses the display device of claim 2, wherein the third channel area (CH5 of ACT5) and the fourth channel area (CH6 of ACT6) are disposed in a third semiconductor layer (SC3) disposed on the first semiconductor layer (Fig. 5 and paragraphs 164-166)).
In regards to claim 4, Kim discloses the display device of claim 3, wherein the first semiconductor layer (SC2) is disposed between the second semiconductor layer (SC1) and the third semiconductor layer (SC3) (Fig. 5 and paragraphs 137-138).
Allowable Subject Matter
Claims 5-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Park et al (US 2023/0157088) discloses a display device and method of fabricating the same. The display device comprises a substrate, a first semiconductor layer, a first gate insulating layer, a first gate electrode dispose, a first interlayer insulating layer, a first oxide semiconductor layer, a second gate insulating layer and a second gate electrode sequentially disposed on the substrate, spacers disposed on side surfaces of the second gate electrode, and a second interlayer insulating layer disposed on the spacers, wherein each of the spacers comprises a first spacer disposed to contact a side surface of the second gate electrode and a second spacer disposed on the first spacer. A concentration of hydrogen included in the first spacer is lower than a concentration of hydrogen included in the second spacer.
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/MICHAEL PERVAN/Primary Examiner, Art Unit 2629 March 12, 2026