DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 3-5 are rejected under 35 U.S.C. 102(a) (1) as being anticipated by
Kunz et al. (US 2003/0189443 and Kunz hereinafter)
Regarding claim 1, Kunz discloses a semiconductor device, comprising: a bias generating circuit [101] comprising a voltage doubling circuit [par. 0038; see fig. 6/fig. 8], wherein the bias generating circuit is operatively coupled to a level shifting circuit [103] and configured to: generate, via the voltage doubling circuit, a bias voltage [PBIAS/107] substantially higher than a voltage of an input signal [IN] corresponding to a first voltage domain [VDD-1X, fig. 9]; and provide the bias voltage to at least one transistor of the level shifting circuit [fig. 8], causing the level shifting circuit to generate an output voltage [106, fig. ] in a second voltage domain [VDD-5X, fig. 8] different from the first voltage domain.
Regarding claim 3, Kunz discloses wherein the voltage doubling circuit [figs. 9B-9C] comprises a capacitor [C5/C6, figs. 9B-9C], and wherein the bias generating circuit is further configured to provide the bias voltage [PBIAS/NBIAS] at a first terminal of the capacitor.
Regarding claim 4, Kunz discloses wherein the bias generating circuit is further configured to receive the input signal [HV-VDD, figs. 9B-9C] at a second terminal of the capacitor.
Regarding claim 5, Kunz discloses wherein the second terminal of the capacitor is coupled to at least one second transistor of the level shifting circuit [fig. 8].
Claims 1-2, 6, 9 and 19-20 are rejected under 35 U.S.C. 102(a) (1) as being anticipated by Chen et al. (TW 200731667A and Chen hereinafter)
Regarding claim 1, Chen discloses a semiconductor device [see fig. 5], comprising: a bias generating circuit [502/504] comprising a voltage doubling circuit [pages 38-39], wherein the bias generating circuit is operatively coupled to a level shifting circuit [506] and configured to: generate, via the voltage doubling circuit, a bias voltage [VC, fig. 6] substantially higher than a voltage of an input signal [VA] corresponding to a first voltage domain [VCCK]; and provide the bias voltage to at least one transistor of the level shifting circuit [fig. 8], causing the level shifting circuit to generate an output voltage [OUT ] in a second voltage domain [VCC1] different from the first voltage domain.
Regarding claim 2, Chen discloses wherein the bias generating circuit is further configured to provide the bias voltage to a thick-oxide gate of the at least one transistor [532/540].
Regarding claim 6, Chen discloses wherein the bias generating circuit is further configured to provide a second bias voltage [504] to at least one second transistor [540] of the level shifting circuit, the second bias voltage being a logical inversion [/DATA] of the bias voltage.
Regarding claim 9, Chen discloses wherein the bias generating circuit comprises a plurality of inverters [fig. 5].
Regarding claim 19, Chen discloses a method [fig. 5], comprising: receiving an input signal [DATA] corresponding to a first voltage source [VCCK] of a first voltage domain; generating, using a voltage doubling circuit [502], a bias voltage [VC] based on the input signal and using the first voltage source; and providing the bias voltage to a thick-oxide transistor [532] of a level shifting circuit [506], causing the level shifting circuit to generate an output voltage [OUT] in a second voltage [VCCI] domain different from the first voltage domain.
Regarding claim 20, Chen discloses further comprising: generating a second bias voltage [voltage 504] as a logical inversion [/DATA] of the bias voltage
Claims 10-11 are rejected under 35 U.S.C. 102(a) (1) as being anticipated by Proebsting et al. (US 5737267 and Proebsting hereinafter)
Regarding claim 10, Proebsting discloses a circuit [fig. 4], comprising: a pair of cross-coupled NMOS transistors [M4-M7], each NMOS transistor of the pair having a respective first source/drain terminal [drain/source M4-M7] coupled to a supply voltage [VCC] of a first voltage domain; a first capacitor [C1] receiving a first signal [voltage at node N5] and coupled to a second source/drain terminal of a first NMOS transistor of the pair [source/drain terminal M4 and M7]; and a second capacitor [C2] receiving a second signal [voltage at node N6] and coupled to a second source/drain terminal of a second NMOS transistor of the pair [source/drain terminal M5 and M6], wherein the first capacitor generates a bias voltage [VG] based on the first signal.
Regarding claim 11, Proebsting discloses wherein the second signal is a logical inversion [using 400] of the first signal.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. Claims 12-19 are rejected under 35 U.S.C. 103 as being unpatentable over Proebsting in view of Chen et al.
Regarding claim 13, Proebsting discloses all the features with respect to claim 10 as indicated above. Proebsting does not explicitly disclose a level shifter including: a first PMOS transistor and a second PMOS transistor, the first PMOS transistor and the second PMOS transistor sourced with a second supply voltage greater than the supply voltage, the first PMOS transistor gated with a drain voltage of the second PMOS transistor, the second PMOS transistor gated with a drain voltage of the first PMOS transistor.
However, Chen discloses [fig. 5] a level shifter [506] including: a first PMOS transistor [534] and a second PMOS transistor [542], the first PMOS transistor and the second PMOS transistor sourced with a second supply voltage [VCC1] greater than a supply voltage [VCCK], the first PMOS transistor gated with a drain voltage of the second PMOS transistor [drain 542], the second PMOS transistor gated with a drain voltage of the first PMOS transistor [drain 534]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus of Proebsting by incorporating level shifter as taught in Chen in order to utilize known level shifter.
Regarding claim 14, Proebsting in view of Chen discloses wherein the first PMOS transistor and the second PMOS transistor each comprise a respective thick-oxide gate [page 29].
Regarding claim 15, Proebsting in view of Chen discloses further comprising a diode-connected transistor [M7, fig. 4 of Proebsting] in parallel with the first NMOS transistor of the pair [M4].
Regarding claim 16, Proebsting in view of Chen discloses wherein the diode-connected transistor is a first diode-connected transistor [M7], and further comprising a second diode-connected transistor [M6] in parallel with the second NMOS transistor of the pair [M5].
Regarding claim 17, Proebsting in view of Chen discloses wherein the first capacitor generates a second bias voltage [voltage 504] based on the first signal, the second bias voltage being a logical inversion [/DATA] of the bias voltage.
Regarding claim 18, Proebsting in view of Chen discloses wherein the bias voltage is provided to a thick-oxide transistor [540] and the first signal is provided to a thin-oxide transistor [538].
Regarding claim 12, Proebsting discloses all the features with respect to claim 10 as indicated above. Proebsting further discloses the first signal is generated by a first inverter [400]. Proebsting does not explicitly disclose wherein the first signal is generated by the second signal is generated by a second inverter.
However, in the same field of endeavor, Chen discloses first signal [VA, fig. 5] is generated by a first inverter [528] and second signal [output of 536] is generated by a second inverter [536]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus of Proebsting by incorporating second inverter as taught in Chen in order to provides the inverted output signal.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Kunz et al. in view of Proebsting.
Regarding claim 7, Kunz discloses all the features with respect to claim 1 as indicated above. Kunz does not explicitly disclose wherein the bias generating circuit comprises a cross-coupled pair of transistors.
However, Proebsting discloses the bias generating circuit [200, fig. 4] comprises a cross-coupled pair of transistors [M4 and M5]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus of Kunz by incorporating bias generating circuit as taught in Proebsting in order to improve drive capability.
Regarding claim 8, Kunz in view of Proebsting discloses wherein the bias generating circuit comprises diode-connected transistor [M7, fig. 4] in parallel with a first transistor [M4] of the cross-coupled pair of transistors.
Conclusion
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/METASEBIA T RETEBO/ Primary Examiner, Art Unit 2836
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