DETAILED ACTION
This action is in response to communications: Preliminary-Amendment filed August 6, 2025.
Claims 23-42 are pending in this case. Claims 1-22 have been newly cancelled. Claims 23-42 have been newly added. This action is made Non-Final.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on May 2, 2025, August 6, 2025, January 14, 2026, and May 16, 2026 were filed on/after the filing date of the application on May 2, 2025. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Drawings
The drawings were received on May 2, 2025. These drawings are accepted.
Double Patenting
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a non-statutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 23-41 are rejected on the ground of non-statutory double patenting as being unpatentable over claims 1-19 of U.S. Patent No. 12,299,769. Although the claims at issue are not identical, they are not patentably distinct from each other as shown in the tables below.
Present Application #19/197,684
23
24
25
26
27
28
29
30
31
U.S. Patent #12,299,769
1
2
3
4
5
6
7
8
9
Present Application #19/197,684
32
33
34
35
36
37
38
39
40
41
U.S. Patent #12,299,769
10
11
12
13
14
15
16
17
18
19
Present Application #19/197,684 Claim 23
U.S. Patent #12,299,769 Claim 1
A system, comprising:
A system, comprising:
a plurality of parallel processing devices,
a plurality of graphics processing devices,
wherein each parallel processing device of the plurality of parallel processing devices includes a respective quantity of active physical resources;
wherein each graphics processing device of the plurality of graphics processing devices includes a respective quantity of active physical resources;
a command processor coupled to the plurality of parallel processing devices; and
a command processor coupled to the plurality of graphics processing devices; and
a dispatch controller of the command processor to dynamically assign each workgroup of a plurality of workgroups to a respective parallel processing device for execution,
a dispatch controller of the command processor to dynamically assign each workgroup of a plurality of workgroups to a respective graphics processing device for execution,
the dynamic assignment based at least in part on an indication of the quantity of active physical resources associated with the respective parallel processing device.
the dynamic assignment based at least in part on an indication of the quantity of active physical resources associated with the respective graphics processing device.
Claim 23 of the present application differs from claim 1 of the patent application in that claim 23 of the present application is broader in scope than claim 1 of the patent application, thus encompasses that of the patent application.
Present Application #19/197,684 Claim 24
U.S. Patent #12,299,769 Claim 2
The system of claim 23, wherein
The graphics processing device of claim 1, wherein
the indication of the respective quantity of active physical resources associated with the respective parallel processing device indicates a respective quantity of shader engines associated with the respective parallel processing device.
the indication of the respective quantity of active physical resources associated with the respective graphics processing device indicates a respective quantity of shader engines associated with the respective graphics processing device.
Present Application #19/197,684 Claim 25
U.S. Patent #12,299,769 Claim 3
The system of claim 23, wherein
The graphics processing device of claim 1, wherein
the dispatch controller of the command processor is further to receive, from a first parallel processing device of the plurality of parallel processing device, one or more indications of active physical resources for the respective parallel processing device.
the dispatch controller of the command processor is further to receive, from a first graphics processing device of the plurality of graphics processing device, one or more indications of active physical resources for the respective graphics processing device.
Present Application #19/197,684 Claim 26
U.S. Patent #12,299,769 Claim 4
The system of claim 23, wherein
The graphics processing device of claim 1, wherein
to dynamically assign each workgroup to a respective parallel processing device includes to dynamically assign each workgroup to a shader engine of a respective parallel processing device via a shader processor input (SPI) associated with the shader engine,
to dynamically assign each workgroup to a respective graphics processing device includes to dynamically assign each workgroup to a shader engine of a respective graphics processing device via a shader processor input (SPI) associated with the shader engine,
the dynamic assignment based at least in part on an indication of available physical resources associated with the shader engine.
the dynamic assignment based at least in part on an indication of available physical resources associated with the shader engine.
Present Application #19/197,684 Claim 27
U.S. Patent #12,299,769 Claim 5
The system of claim 26, wherein
The graphics processing device of claim 4, wherein
the indication of available physical resources associated with the shader engine includes status information received by the command processor from the associated SPI, and
the indication of available physical resources associated with the shader engine includes status information received by the command processor from the associated SPI, and
wherein the status information includes an indication of current progress of the shader engine with respect to processing one or more workgroups assigned to the shader engine.
wherein the status information includes an indication of current progress of the shader engine with respect to processing one or more workgroups assigned to the shader engine.
Present Application #19/197,684 Claim 28
U.S. Patent #12,299,769 Claim 6
The system of claim 27, wherein
The graphics processing device of claim 5, wherein
the status information includes an indication of one or more available workgroup assignment slots of the shader engine.
the status information includes an indication of one or more available workgroup assignment slots of the shader engine.
Present Application #19/197,684 Claim 29
U.S. Patent #12,299,769 Claim 7
The system of claim 23, wherein
The graphics processing device of claim 1, wherein
the command processor is further to maintain current status information for each shader engine of the plurality of parallel processing devices based at least in part on one or more indications of available physical resources respectively associated with each parallel processing device of the plurality of parallel processing devices.
the command processor is further to maintain current status information for each shader engine of the plurality of graphics processing devices based at least in part on one or more indications of available physical resources respectively associated with each graphics processing device of the plurality of graphics processing devices.
Present Application #19/197,684 Claim 30
U.S. Patent #12,299,769 Claim 8
The system of claim 23, wherein
The system of claim 1, wherein
each parallel processing device of the plurality of parallel processing devices comprises a chiplet.
each graphics processing device of the plurality of graphics processing devices comprises a graphics processing unit (GPU) chiplet.
Present Application #19/197,684 Claim 31
U.S. Patent #12,299,769 Claim 9
The system of claim 23, wherein
The system of claim 1, wherein
each dispatch controller of each parallel processing device of the plurality of parallel processing devices coordinates with one or more other dispatch controllers of one or more other parallel processing devices of the plurality of parallel processing devices to dynamically assign workgroups.
each dispatch controller of each graphics processing device of the plurality of graphics processing devices coordinates with one or more other dispatch controllers of one or more other graphics processing devices of the plurality of graphics processing devices to dynamically assign workgroups.
Present Application #19/197,684 Claim 32
U.S. Patent #12,299,769 Claim 10
A method comprising:
A method comprising:
generating, based on one or more received commands, a plurality of workgroups for assignment to a plurality of parallel processing devices for processing,
generating, based on one or more received commands, a plurality of workgroups for assignment to a plurality of graphics processing devices for processing,
each parallel processing device of the plurality of parallel processing devices including a respective quantity of active physical resources; and
each graphics processing device of the plurality of graphics processing devices including a respective quantity of active physical resources; and
dynamically assigning each workgroup of the plurality of workgroups to a respective parallel processing device for execution,
dynamically assigning each workgroup of the plurality of workgroups to a respective graphics processing device for execution,
the dynamic assigning based at least in part on an indication of the quantity of active physical resources associated with the respective parallel processing device.
the dynamic assigning based at least in part on an indication of the quantity of active physical resources associated with the respective graphics processing device.
Claim 32 of the present application differs from claim 10 of the patent application in that claim 32 of the present application is broader in scope than claim 10 of the patent application, thus encompasses that of the patent application.
Present Application #19/197,684 Claim 33
U.S. Patent #12,299,769 Claim 11
The method of claim 32, wherein
The method of claim 10, wherein
the indication of the quantity of active physical resources associated with the respective parallel processing device indicates a respective quantity of active compute units associated with shader engines of the parallel processing device.
the indication of the quantity of active physical resources associated with the respective graphics processing device indicates a respective quantity of active compute units associated with shader engines of the graphics processing device.
Present Application #19/197,684 Claim 34
U.S. Patent #12,299,769 Claim 12
The method of claim 32, further comprising
The method of claim 10, further comprising
receiving, by a dispatch controller of a command processor, one or more indications of active physical resources for a first shader engine of the plurality of parallel processing devices.
receiving, by a dispatch controller of a command processor, one or more indications of active physical resources for a first shader engine of the plurality of graphics processing devices.
Present Application #19/197,684 Claim 35
U.S. Patent #12,299,769 Claim 13
The method of claim 34, wherein
The method of claim 12, wherein
dynamically assigning each workgroup to a respective parallel processing device includes dynamically assigning one or more workgroups to the first shader engine via a shader processor input (SPI) associated with the first shader engine based at least in part on an indication of available physical resources associated with the first shader engine.
dynamically assigning each workgroup to a respective graphics processing device includes dynamically assigning one or more workgroups to the first shader engine via a shader processor input (SPI) associated with the first shader engine based at least in part on an indication of available physical resources associated with the first shader engine.
Present Application #19/197,684 Claim 36
U.S. Patent #12,299,769 Claim 14
The method of claim 35, wherein
The method of claim 13, wherein
the indication of available physical resources includes status information received by a command processor from the associated SPI, and
the indication of available physical resources includes status information received by a command processor from the associated SPI, and
wherein the status information includes an indication of current progress of the first shader engine in processing one or more workgroups assigned to the first shader engine.
wherein the status information includes an indication of current progress of the first shader engine in processing one or more workgroups assigned to the first shader engine.
Present Application #19/197,684 Claim 37
U.S. Patent #12,299,769 Claim 15
The method of claim 36, wherein
The method of claim 14, wherein
the status information includes an indication of one or more available workgroup assignment slots of the first shader engine.
the status information includes an indication of one or more available workgroup assignment slots of the first shader engine.
Present Application #19/197,684 Claim 38
U.S. Patent #12,299,769 Claim 16
The method of claim 32, further comprising
The method of claim 10, further comprising
maintaining, by a command processor, current status information for each shader engine of the plurality of parallel processing devices based at least in part on one or more indications of active physical resources respectively associated with each shader engine.
maintaining, by a command processor, current status information for each shader engine of the plurality of graphics processing devices based at least in part on one or more indications of active physical resources respectively associated with each shader engine.
Present Application #19/197,684 Claim 39
U.S. Patent #12,299,769 Claim 17
The method of claim 32, wherein
The method of claim 10, wherein
each parallel processing device of the plurality of parallel processing devices comprises a chiplet.
each graphics processing device of the plurality of graphics processing devices comprises a graphics processing unit (GPU) chiplet.
Present Application #19/197,684 Claim 40
U.S. Patent #12,299,769 Claim 18
The method of claim 32, wherein
The method of claim 10, wherein
each parallel processing device of the plurality of parallel processing devices comprises a dispatch controller, and
each graphics processing device of the plurality of graphics processing devices comprises a dispatch controller, and
wherein the method further comprises coordinating between the dispatch controllers of the plurality of parallel processing devices to dynamically assign the plurality of workgroups.
wherein the method further comprises coordinating between the dispatch controllers of the plurality of graphics processing devices to dynamically assign the plurality of workgroups.
Present Application #19/197,684 Claim 41
U.S. Patent #12,299,769 Claim 19
A non-transitory computer-readable medium storing instructions that, when executed by one or more processors, causes the one or more processors to:
A non-transitory computer-readable medium storing instructions that, when executed by one or more processors, causes the one or more processors to:
generate, based on one or more received commands, a plurality of workgroups for assignment to a plurality of parallel processing devices for processing,
generate, based on one or more received commands, a plurality of workgroups for assignment to a plurality of graphics processing devices for processing,
each parallel processing device of the plurality of parallel processing devices including a respective quantity of active physical resources; and
each graphics processing device of the plurality of graphics processing devices including a respective quantity of active physical resources; and
dynamically assign each workgroup of the plurality of workgroups to a respective parallel processing device for execution,
dynamically assign each workgroup of the plurality of workgroups to a respective graphics processing device for execution,
the dynamic assignment based at least in part on an indication of the quantity of active physical resources associated with the respective parallel processing device.
the dynamic assignment based at least in part on an indication of the quantity of active physical resources associated with the respective graphics processing device.
Claim 41 of the present application differs from claim 19 of the patent application in that claim 41 of the present application is broader in scope than claim 19 of the patent application, thus encompasses that of the patent application.
Claims 23-41 are rejected on the ground of non-statutory double patenting as being unpatentable over claims 1-16 of U.S. Patent No. 11,941,723. Although the claims at issue are not identical, they are not patentably distinct from each other as shown in the tables below.
Present Application #19/197,684
23
24
25
26
27
28
29
30
31
U.S. Patent #11,941,723
1,15
2
3
4
4,5
6
7
16
15
Present Application #19/197,684
32
33
34
35
36
37
38
39
40
41
U.S. Patent #11,941,723
8,15
9
10
11
11,12
13
14
16
15
8
Present Application #19/197,684 Claim 23
U.S. Patent #11,941,723 Claim 1
A system, comprising:
A graphics processing device, comprising:
a plurality of parallel processing devices,
a plurality of shader engines,
wherein each parallel processing device of the plurality of parallel processing devices includes a respective quantity of active physical resources;
wherein each shader engine of the plurality of shader engines includes a respective quantity of active physical resources;
a command processor coupled to the plurality of parallel processing devices; and
a command processor coupled to the plurality of shader engines; and
a dispatch controller of the command processor to dynamically assign each workgroup of a plurality of workgroups to a respective parallel processing device for execution,
a dispatch controller of the command processor to dynamically assign each workgroup of a plurality of workgroups to a respective shader engine for execution,
the dynamic assignment based at least in part on an indication of the quantity of active physical resources associated with the respective parallel processing device.
the dynamic assignment based at least in part on an indication of the quantity of active physical resources associated with the respective shader engine.
Claim 23 of the present application differs from claim 1 of the patent application in that claim 23 of the present application is broader in scope than claim 1 of the patent application, thus encompasses that of the patent application.
Present Application #19/197,684 Claim 23
U.S. Patent #11,941,723 Claim 15
A system, comprising:
A system, comprising:
a plurality of parallel processing devices,
a plurality of graphics processing devices,
wherein each parallel processing device of the plurality of parallel processing devices includes a respective quantity of active physical resources;
each graphics processing device of the plurality of graphics processing devices including: a plurality of shader engines, wherein each shader engine of the plurality of shader engines includes a respective quantity of active physical resources;
a command processor coupled to the plurality of parallel processing devices; and
a command processor coupled to the plurality of shader engines; and
a dispatch controller of the command processor to dynamically assign each workgroup of a plurality of workgroups to a respective parallel processing device for execution,
a dispatch controller of the command processor to dynamically assign each workgroup of a plurality of workgroups to a respective shader engine for execution,
the dynamic assignment based at least in part on an indication of the quantity of active physical resources associated with the respective parallel processing device.
the dynamic assignment based at least in part on an indication of the quantity of active physical resources associated with the respective shader engine;
wherein each dispatch controller of each graphics processing device of the plurality of graphics processing devices coordinates with one or more other dispatch controllers of one or more other graphics processing devices of the plurality of graphics processing devices to dynamically assign workgroups.
Claim 23 of the present application differs from claim 15 of the patent application in that claim 23 of the present application is broader in scope than claim 15 of the patent application, thus encompasses that of the patent application.
Present Application #19/197,684 Claim 24
U.S. Patent #11,941,723 Claim 2
The system of claim 23, wherein
The graphics processing device of claim 1, wherein
the indication of the respective quantity of active physical resources associated with the respective parallel processing device indicates a respective quantity of shader engines associated with the respective parallel processing device.
the indication of the respective quantity of active physical resources associated with the respective shader engine indicates a respective quantity of active compute units associated with the respective shader engine.
Present Application #19/197,684 Claim 25
U.S. Patent #11,941,723 Claim 3
The system of claim 23, wherein
The graphics processing device of claim 1, wherein
the dispatch controller of the command processor is further to receive, from a first parallel processing device of the plurality of parallel processing device, one or more indications of active physical resources for the respective parallel processing device.
the dispatch controller of the command processor is further to receive, from a first shader engine of the plurality of shader engines, one or more indications of active physical resources for the respective shader engine.
Present Application #19/197,684 Claim 26
U.S. Patent #11,941,723 Claim 4
The system of claim 23, wherein
The graphics processing device of claim 1, wherein
to dynamically assign each workgroup to a respective parallel processing device includes to dynamically assign each workgroup to a shader engine of a respective parallel processing device via a shader processor input (SPI) associated with the shader engine, the dynamic assignment based at least in part on an indication of available physical resources associated with the shader engine.
to dynamically assign each workgroup to a respective shader engine includes to dynamically assign each workgroup to a respective shader engine via a shader processor input (SPI) associated with the respective shader engine based at least in part on an indication of available physical resources associated with the respective shader engine that includes status information received by the command processor from the associated SPI.
Present Application #19/197,684 Claim 27
U.S. Patent #11,941,723 Claims 4 and 5
The system of claim 26, wherein
The graphics processing device of claim 1/4, wherein
wherein to dynamically assign each workgroup to a respective shader engine includes to dynamically assign each workgroup to a respective shader engine via a shader processor input (SPI) associated with the respective shader engine based at least in part on (claim 4)…
the indication of available physical resources associated with the shader engine includes status information received by the command processor from the associated SPI, and
an indication of available physical resources associated with the respective shader engine that includes status information received by the command processor from the associated SPI (claim 4)…
wherein the status information includes an indication of current progress of the shader engine with respect to processing one or more workgroups assigned to the shader engine.
wherein the status information includes an indication of current progress of the respective shader engine with respect to processing one or more workgroups assigned to the respective shader engine (claim 5)
Present Application #19/197,684 Claim 28
U.S. Patent #11,941,723 Claim 6
The system of claim 27, wherein
The graphics processing device of claim 4, wherein
the status information includes an indication of one or more available workgroup assignment slots of the shader engine.
the status information includes an indication of one or more available workgroup assignment slots of the respective shader engine.
Present Application #19/197,684 Claim 29
U.S. Patent #11,941,723 Claim 7
The system of claim 23, wherein
The graphics processing device of claim 1, wherein
the command processor is further to maintain current status information for each shader engine of the plurality of parallel processing devices based at least in part on one or more indications of available physical resources respectively associated with each parallel processing device of the plurality of parallel processing devices.
the command processor is further to maintain current status information for each shader engine of the plurality of shader engines based at least in part on one or more indications of available physical resources respectively associated with each of the plurality of shader engines.
Present Application #19/197,684 Claim 30
U.S. Patent #11,941,723 Claim 16
The system of claim 23, wherein
The system of claim 15, wherein
each parallel processing device of the plurality of parallel processing devices comprises a chiplet.
each graphics processing device of the plurality of graphics processing devices comprises a graphics processing unit (GPU) chiplet.
Present Application #19/197,684 Claim 31
U.S. Patent #11,941,723 Claim 15
The system of claim 23, wherein
A system…wherein
each dispatch controller of each parallel processing device of the plurality of parallel processing devices coordinates with one or more other dispatch controllers of one or more other parallel processing devices of the plurality of parallel processing devices to dynamically assign workgroups.
each dispatch controller of each graphics processing device of the plurality of graphics processing devices coordinates with one or more other dispatch controllers of one or more other graphics processing devices of the plurality of graphics processing devices to dynamically assign workgroups.
Present Application #19/197,684 Claim 32
U.S. Patent #11,941,723 Claim 8
A method comprising:
A method comprising:
generating, based on one or more received commands, a plurality of workgroups for assignment to a plurality of parallel processing devices for processing,
generating, based on one or more received commands, a plurality of workgroups for assignment to a plurality of shader engines for processing,
each parallel processing device of the plurality of parallel processing devices including a respective quantity of active physical resources; and
each shader engine of the plurality of shader engines including a respective quantity of active physical resources; and
dynamically assigning each workgroup of the plurality of workgroups to a respective parallel processing device for execution,
dynamically assigning each workgroup of the plurality of workgroups to a respective shader engine for execution,
the dynamic assigning based at least in part on an indication of the quantity of active physical resources associated with the respective parallel processing device.
the dynamic assigning based at least in part on an indication of the quantity of active physical resources associated with the respective shader engine.
Claim 32 of the present application differs from claim 8 of the patent application in that claim 32 of the present application is broader in scope than claim 8 of the patent application, thus encompasses that of the patent application.
NOTE: Claim 32 of the present application is similar in scope to claim 1 of the present application, thus may be rejected under similar as claim 1, e.g. against claim 15 of the patent application.
Present Application #19/197,684 Claim 33
U.S. Patent #11,941,723 Claim 9
The method of claim 32, wherein
The method of claim 8, wherein
the indication of the quantity of active physical resources associated with the respective parallel processing device indicates a respective quantity of active compute units associated with shader engines of the parallel processing device.
the indication of the quantity of the quantity of active physical resources associated with the respective shader engine indicates a respective quantity of active compute units associated with the respective shader engine.
Present Application #19/197,684 Claim 34
U.S. Patent #11,941,723 Claim 10
The method of claim 32, further comprising
The method of claim 8, further comprising
receiving, by a dispatch controller of a command processor, one or more indications of active physical resources for a first shader engine of the plurality of parallel processing devices.
receiving, by a dispatch controller of a command processor, one or more indications of active physical resources for a first shader engine of the plurality of shader engines from the first shader engine.
Present Application #19/197,684 Claim 35
U.S. Patent #11,941,723 Claim 11
The method of claim 34, wherein
The method of claim 8, wherein
dynamically assigning each workgroup to a respective parallel processing device includes dynamically assigning one or more workgroups to the first shader engine via a shader processor input (SPI) associated with the first shader engine based at least in part on an indication of available physical resources associated with the first shader engine.
dynamically assigning each workgroup to a respective shader engine includes dynamically assigning each workgroup to a respective shader engine via a shader processor input (SPI) associated with the respective shader engine based at least in part on an indication of available physical resources associated with the respective shader engine that includes status information received by a command processor from the associated SPI.
Present Application #19/197,684 Claim 36
U.S. Patent #11,941,723 Claims 11 and 12
The method of claim 35, wherein
The method of claim 8/11, wherein
dynamically assigning each workgroup to a respective shader engine includes dynamically assigning each workgroup to a respective shader engine via a shader processor input (SPI) associated with the respective shader engine based at least in part on (claim 11)…
the indication of available physical resources includes status information received by a command processor from the associated SPI, and
an indication of available physical resources associated with the respective shader engine that includes status information received by a command processor from the associated SPI (claim 11)…
wherein the status information includes an indication of current progress of the first shader engine in processing one or more workgroups assigned to the first shader engine.
wherein the status information includes an indication of current progress of the respective shader engine in processing one or more workgroups assigned to the respective shader engine (claim 12).
Present Application #19/197,684 Claim 37
U.S. Patent #11,941,723 Claim 13
The method of claim 36, wherein
The method of claim 11, wherein
the status information includes an indication of one or more available workgroup assignment slots of the first shader engine.
the status information includes an indication of one or more available workgroup assignment slots of the respective shader engine.
Present Application #19/197,684 Claim 38
U.S. Patent #11,941,723 Claim 14
The method of claim 32, further comprising
The method of claim 8, further comprising
maintaining, by a command processor, current status information for each shader engine of the plurality of parallel processing devices based at least in part on one or more indications of active physical resources respectively associated with each shader engine.
maintaining, by a command processor, current status information for each shader engine of the plurality of shader engines based at least in part on one or more indications of active physical resources respectively associated with each of the plurality of shader engines.
Present Application #19/197,684 Claim 39
U.S. Patent #11,941,723 Claim 16
The method of claim 32, wherein
The system of claim 15, wherein
each parallel processing device of the plurality of parallel processing devices comprises a chiplet.
each graphics processing device of the plurality of graphics processing devices comprises a graphics processing unit (GPU) chiplet.
Present Application #19/197,684 Claim 40
U.S. Patent #11,941,723 Claim 15
The method of claim 32, wherein
A system…wherein…
each parallel processing device of the plurality of parallel processing devices comprises a dispatch controller, and
…each dispatch controller of each graphics processing device of the plurality of graphics processing devices
wherein the method further comprises coordinating between the dispatch controllers of the plurality of parallel processing devices to dynamically assign the plurality of workgroups.
coordinates with one or more other dispatch controllers of one or more other graphics processing devices of the plurality of graphics processing devices to dynamically assign workgroups.
Present Application #19/197,684 Claim 41
U.S. Patent #11,941,723 Claim 8
A non-transitory computer-readable medium storing instructions that, when executed by one or more processors, causes the one or more processors to:
A method comprising:
generate, based on one or more received commands, a plurality of workgroups for assignment to a plurality of parallel processing devices for processing,
generating, based on one or more received commands, a plurality of workgroups for assignment to a plurality of shader engines for processing,
each parallel processing device of the plurality of parallel processing devices including a respective quantity of active physical resources; and
each shader engine of the plurality of shader engines including a respective quantity of active physical resources; and
dynamically assign each workgroup of the plurality of workgroups to a respective parallel processing device for execution,
dynamically assigning each workgroup of the plurality of workgroups to a respective shader engine for execution,
the dynamic assignment based at least in part on an indication of the quantity of active physical resources associated with the respective parallel processing device.
the dynamic assigning based at least in part on an indication of the quantity of active physical resources associated with the respective shader engine.
Claim 41 of the present application differs from claim 8 of the patent application in that claim 41 of the present application is broader in scope than claim 8 of the patent application, thus encompasses that of the patent application. Additionally, claim 41 of the present application is directed to “a non-transitory computer-readable medium storing instructions that, when executed by one or more processors, causes the one or more processors to” perform the method as described, where claim 8 of the patent application is directed to a method. However, it is well known that. in a typical computer system, the steps of a method may be implemented as instructions stored on a computer-readable medium and further executed by a processor, thus yielding predictable results.
Allowable Subject Matter
Claims 23-41 would be allowable if the Double Patenting rejection set forth above may be overcome.
Claim 42 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The present invention relates to a system and method of dynamic dispatch for workgroup distribution, more specifically, dynamically assigning workgroups to respective graphics processing devices based on an indication of the quantity of active physical resources associated with the respective graphics processing devices.
Prior art includes:
Havlir et al. (US 10,901,777)(cited in the Information Disclosure Statement (IDS) filed May 2, 2025) disclose a system (Figure 11, device 1100), comprising: a plurality of parallel processing devices (graphics processing unit (GPU) 150, where column 18, lines 27-28 notes GPU 150 may be one or more GPUs, thus a plurality of GPUs), wherein each parallel processing device of the plurality of parallel processing devices (e.g. GPU 150, further illustrated in Figure 1B, 2A, 2B, and 4, and further comprising shaders 250A-250M, where column 3, lines 42-51 notes GPU and components therein may process graphics data in parallel) includes a respective quantity of active physical resources (column 4, lines 12-13 notes each shader, such as shaders 250, may include multiple pipelines for processing data in parallel, where Figure 5 and associated text notes method of context switching, where column 12, lines 18-20 notes process includes a number of active shaders); a command processor (e.g. global workload parser 210) coupled to the plurality of parallel processing devices (coupled to plurality of shaders 250 of GPU 150); and a dispatch controller of the command processor (e.g. distributed workload parser(s) 220A-220N communicatively coupled to global workload parser 210, where column 5, lines 65-67 notes the global workload parser 210 and distributed workload parsers 220 may be on the same integrated circuit) to dynamically assign each workgroup of a plurality of workgroups to a respective parallel processing device for execution (e.g. dynamically assign work, pixel work, vertex work, and compute work as workgroups for execution to each of shaders 250), the dynamic assignment based at least in part on an indication of available physical resources associated with the respective parallel processing device (e.g. based on available entries in queues 414 tracked by queue credit tracker 412 and available resources tracked by resource tracker 418 of distributed workload parsers 220, further tracked by global workload parser 210), (Figure 4 and associated text, e.g. column 9, lines 43 thru column 10, lines 47 notes global parser to track each of distributed workload parsers 220, where column 10, lines 48 thru column 11, lines 7 notes each of distributed workload parsers 220 further includes a queue credit tracker 412 configured to track a queue space in queues 414, where distributed workload parsers 220 are configured not to send workgroups that would use the last space in a queue to prevent stalling on kernel terminates, the distributed workload parsers 220 also include resource tracker 418 configured to track the resources of each shader 250, e.g. the number of outstanding work items sent to each shader, and select a shader for each workgroup based on the tracked resources);
Bourd et al. (US 10,026,145) disclose a system and method of sharing resources on a shader processor of a graphics processing unit (GPU) based on availability of the resources (Figure 4);
Bose et al. (US 8,296,773) disclose a system and method of dynamically shutting down cores and assigning threads of a workload to an active number of cores remaining active (Figures 2 and 3);
Farazmand (US 2017/0199558)(cited in the Information Disclosure Statement (IDS) filed May 2, 2025) discloses a system where a respective quantity of active compute units associated with each of the at least some shader engines ([0110] notes each of energy equations 70 may, in addition to model parameters that correspond with workload dependent events, further include independent variables that correspond to the number of active processing cores of GPU 12, such as the number of active cores of shader core 26, the number of active cores of texture units/processors of GPU 12); and
Jiao et al. (US 2007/0091088) and (US 2007/0091089)(cited in the Information Disclosure Statement (IDS) filed May 2, 2025) disclose systems and methods of managing and performing dynamic allocation or reallocation of processing resources among a vertex shader, geometry shader, and pixel shader of a graphics processing unit (GPU).
Although the prior art of record discloses certain features of the claimed invention as outlined above, the prior art of record fails to explicitly teach or suggest, singly or combined, the limitations, “…dynamically assign each workgroup of a plurality of workgroups to a respective parallel processing device for execution, the dynamic assignment based at least in part on an indication of the quantity of active physical resources associated with the respective parallel processing device...” thus does not recite the limitations as recited by independent claims 23, 32, and 41 as a whole.
Regarding dependent claim 42, the prior art of record fails to teach or suggest, singly or combined, the limitations of the claim as recited.
Conclusion
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/JACINTA M CRAWFORD/Primary Examiner, Art Unit 2617
