DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is the initial Office Action based on the application filed 05/05/2025. Claims 1-9 are presented for examination and have been considered below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4 and 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Akahoshi et al., “Partially Fault-tolerant Quantum Computing Architecture with Error-corrected Clifford Gates and Space-time Efficient Analog Rotations,” (“Akahoshi”), in view of Murali et al., “Noise-Adaptive Compiler Mappings for Noisy Intermediate-Scale Quantum Computers,” ASPLOS ’19, pp. 1015–1029 (“Murali”).
Claim 1: Akahoshi teaches a non-transitory computer-readable recording medium storing a computer program that causes a computer to perform a process comprising:
interconnected qubits among a plurality of qubits in a qubit device included in a quantum computer, an order of priority for the qubit pair that is used in a gate operation of a two-qubit rotation gate in an ancilla state generation circuit, the ancilla state generation circuit being used for implementing a phase rotation gate (e.g., Akahoshi teaches the claimed quantum computer including a plurality of interconnected qubits. In Section III.A, Akahoshi explains that physical qubits forming a rotated planar surface code are arranged on vertices of a two-dimensional lattice, with a collection of physical qubits constituting a logical patch. The code distance d is the side length of the lattice, and a surface carrying a logical state is referred to as a logical “patch.” Akahoshi further teaches the claimed ancilla-state generation circuit used for implementing a phase rotation gate. Section IV, “Space-Time Efficient Analog Rotation Gate,” explains that a special ancilla state is generated for implementing analog rotation. More specifically, Section IV.B and Fig. 9 teach preparing the special ancilla state |m_\theta\rangle_L in a four-physical-qubit [[4,1,1,2]] subsystem code. Hadamard and CNOT operations first prepare the encoded state, after which the logical two-qubit rotation R_{Z_0Z_2}(\theta)=e^{-i\theta Z_0Z_2/2} acts on qubits 0 and 2 to generate the ancilla state |m_\theta\rangle_L.);
generating a plurality of arrangement candidates each indicating a candidate of positions of a plurality of qubit groups in the qubit device, the plurality of qubit groups being used in parallel execution of the ancilla state generation circuit (e.g., Akahoshi also teaches parallel execution of the ancilla-state-generation circuit. After describing expansion of the injected ancilla into a surface-code patch, Akahoshi states that the success rate of post-selection can be improved by performing the injection protocol in parallel using empty space in the target patch, after which a successful ancilla state is selected. Section V further teaches multiple qubit groups or logical-patch units used in parallel. Akahoshi states that the ancilla state should be prepared in parallel for each data logical qubit and that four logical patches can be grouped as a unit carrying a data logical qubit and an ancilla qubit for parallel rotation gates. Fig. 16 illustrates an arrangement of multiple such units.);
and
determining to cause the quantum computer to execute the ancilla state generation circuit in parallel using a first plurality of qubit groups at positions indicated by the selected arrangement candidate, in causing the quantum computer to execute a gate operation of the phase rotation gate, wherein the phase rotation gate includes a gate teleportation circuit and an ancilla state generated by the ancilla state generation circuit is input to the gate teleportation circuit (e.g., Akahoshi additionally teaches that different qubit arrangements are possible and should be optimized. Section V explains that logical-qubit arrangement depends upon the computational scheme, that unnecessary overhead can be minimized by finding an optimal arrangement, and that a logical-qubit arrangement optimizer and circuit compiler are needed. Akahoshi further states that some remote CNOT operations cannot be performed in parallel because their ancilla regions overlap and concludes that, to minimize such conflicts, the mapping of the quantum circuit should be optimized. Akahoshi also teaches the claimed gate teleportation. Section IV.A explains that analog rotation is implemented with the special ancilla state, and Section IV.B states that the successfully generated/post-selected ancilla state can be consumed by the gate teleportation circuit of Fig. 7.).
Akahoshi does not expressly teach determining, based on accuracy information indicating error rates of a two-qubit gate operation executed on each qubit pair of a plurality of qubit pairs and selecting an arrangement candidate from the plurality of arrangement candidates, based on orders of priority determined for first qubit pairs that are to be used in the gate operation of the two-qubit rotation gate in execution of the ancilla state generation circuit in the plurality of qubit groups at positions indicated by each of the plurality of arrangement candidates.
However, Murali expressly teaches that CNOT is a two-qubit gate and that physical hardware permits such two-qubit operations only between connected/adjacent qubits. Murali further explains that hardware CNOT error rates vary substantially among physical qubit pairs and that these gate-error measurements are supplied through machine calibration data. Murali’s Fig. 2 labels physical-qubit connections with their respective CNOT gate errors. Section 2 reports substantial spatial and temporal variation in CNOT error rates and explains that the compiler uses these calibration measurements to avoid unreliable regions of the quantum device. Section 3 teaches a noise-aware compiler that automatically generates mappings using machine topology and calibration data. Murali expressly states that the compiler selects a mapping avoiding gates having high error rates and places program qubits at hardware locations having high reliability. Section 3.1, “Optimization-Based Mappings,” is particularly relevant. Murali formulates mapping as a constrained optimization problem whose variables include program-qubit locations and whose constraints incorporate machine error information. For a given mapping, the solver determines the reliability of the program’s CNOT operations and calculates an overall reliability score. For noise-aware variants, the solver maximizes that reliability score over the possible mappings while tracking the error rates associated with particular physical-qubit locations. Murali explains that optimizing the reliability score causes the compiler to place qubits at locations where CNOT errors are low. Section 4.4, “Reliability Constraints,” makes the pair-specific character of the reliability data explicit. Murali computes, for each pair of hardware qubits, the reliability of CNOT execution paths and stores those values in a reliability matrix E^C. Equation (11) associates the reliability g.\epsilon of a given CNOT with the particular hardware-qubit pair to which the control and target are mapped:
g_c=h_1 \land g_t=h_2 \land g.j=h_j
\Rightarrow
g.\epsilon=E^C_{h_1,h_2,j}.
Murali states that the stored reliability includes both the reliability of any required routing operations and the actual CNOT operation. Section 4.5 then selects the physical mapping according to those reliability values. The reliability-oriented objective selects the mapping maximizing gate reliability, and Murali expressly states that optimization places qubits at hardware locations having high CNOT reliability. Murali additionally teaches an ordered priority mechanism in Section 5.2, “Greatest Weighted Edge First.” GreedyE maps interacting qubit-pair edges in descending order of weight; the highest-priority edge is first placed at a hardware location having maximum CNOT/readout reliability, and remaining interacting qubits are assigned to positions maximizing CNOT reliability relative to already mapped qubits. Accordingly, Murali teaches or at least renders obvious the claimed: “order of priority for each qubit pair” because Murali expressly considers pairs/edges in an ordered sequence and selects physical-qubit locations based on pair-specific measured CNOT reliability. Murali also supplies the claimed generation and evaluation of plural arrangement candidates. Its optimization process searches over different assignments of program qubits to physical hardware locations and selects the mapping maximizing reliability. Sections 3 and 3.1 explain that mapping variables are optimized across possible physical locations, resulting in selection of an execution-ready physical mapping.
Therefore, it would have been obvious to one having ordinary skill in the art at the relevant time to modify Akahoshi’s contemplated logical-qubit arrangement optimizer using Murali’s calibration- and reliability-based physical-qubit mapping technique. Akahoshi itself supplies the reason for optimizing placement: ancilla-state generation is error-sensitive; parallel generation is used to improve success; and an optimal arrangement/mapping is desirable to reduce computational overhead and physical conflicts. Murali teaches a known solution to the physical-mapping problem—use measured pair-specific two-qubit-gate error information to avoid unreliable connections and select mappings that maximize gate reliability. Murali’s calibration-aware approach significantly improves program success by adapting physical placement to changing operation-error rates. A skilled artisan therefore would have had reason to apply Murali’s reliability-aware mapping to Akahoshi’s expressly contemplated arrangement optimizer to place the two-qubit operations of Akahoshi’s ancilla-state-generation circuit on more reliable physical-qubit connections, thereby reducing errors and increasing the likelihood of successfully generating the ancilla states used for parallel phase-rotation operations.
Claim 2: Akahoshi and Murali teach the non-transitory computer-readable recording medium according to claim 1, wherein the generating of the plurality of arrangement candidates includes extracting the plurality of qubit groups from a region with predetermined code distance and generating one or more arrangement candidates. For instance, Akahoshi, in Section III.A, defines the rotated planar surface code and states that its code distance d is the length of the side of the lattice. Section IV.B teaches that after the ancilla state passes post-selection it is expanded to a rotated surface-code patch having an arbitrary code distance, specifically illustrating expansion to a d=5 patch in Fig. 12. Section V then forms logical-qubit groups/units from such logical patches and arranges the units for parallel execution. Murali supplies, as discussed for claim 1, the generation/evaluation of multiple possible mappings of such qubit resources. It therefore would have been obvious to generate candidate arrangements composed of Akahoshi’s qubit groups selected from predetermined-code-distance surface-code regions and evaluate their physical positions using Murali’s reliability-based mapping process.
Claim 3: Akahoshi and Murali teach the non-transitory computer-readable recording medium according to claim 1, wherein the selecting of the arrangement candidate includes calculating an evaluation index value for each arrangement candidate of the plurality of arrangement candidates, based on the accuracy information, the evaluation index value indicating a likelihood of failure in generation of the ancilla state, and selecting the arrangement candidate, based on the evaluation index value calculated for the each arrangement candidate. For instance, Murali, in Section 3.1, calculates, for each mapping under consideration, the reliability of the relevant CNOT operations and derives an overall reliability score. The solver then maximizes that score over the available mappings while tracking operation error rates. Section 4.5 similarly defines the reliability objective and selects the mapping maximizing the calculated execution reliability. When Murali’s reliability evaluation is applied specifically to the operations making up Akahoshi’s ancilla-state-generation circuit, the resulting reliability score represents the likelihood that those ancilla-generation operations successfully execute at the corresponding candidate physical locations. Conversely, 1-R, or an equivalent error metric, represents a likelihood of failure. It would have been obvious to use such a reliability/failure score as an evaluation index for candidate physical arrangements because Akahoshi expressly seeks low-error ancilla preparation while Murali expressly teaches selecting physical mappings according to operation-error-derived reliability.
Claim 4: Akahoshi and Murali teach the non-transitory computer-readable recording medium according to claim 3, wherein the selecting of the arrangement candidate includes detecting, for the each arrangement candidate as a calculation-target arrangement candidate, a minimum error rate among qubit pairs included in each qubit group of the plurality of qubit groups included in the calculation-target arrangement candidate, and calculating the evaluation index value based on minimum error rates detected respectively in the plurality of qubit groups in such a manner that the likelihood of failure indicated by the evaluation index value decreases as the minimum error rates decrease. For instance, Murali teaches that physical two-qubit connections have different calibrated error rates and expressly optimizes mappings toward locations having greater CNOT reliability/lower CNOT error. In Section 5.1, an unmapped qubit that interacts with an already mapped qubit is assigned to the position maximizing total reliability. In Section 5.2, GreedyE likewise maps an interacting qubit to the position maximizing CNOT reliability with already mapped qubits. Because for the same two-qubit gate type greater reliability corresponds to lower gate-error probability, selecting the available connection having maximum reliability corresponds to selecting the available physical pair having minimum error. When Murali’s optimization is separately applied to each of Akahoshi’s parallel logical/qubit groups, it would have been obvious to choose the lower-error available pair in each group for the error-sensitive two-qubit operation and to evaluate the overall candidate according to those selected pair reliabilities, because doing so directly advances the references’ stated goal of reducing operation error and improving successful execution.
Claim 6: Akahoshi and Murali teach the non-transitory computer-readable recording medium according to claim 1, wherein the process further includes determining, in executing the ancilla state generation circuit in parallel, that a qubit pair having a minimum error rate in each of the first plurality of qubit groups is a first qubit pair on which the two-qubit rotation gate included in the ancilla state generation circuit is caused to act. For instance, Murali teaches precisely the general physical-mapping principle underlying such a choice: measured CNOT error rates vary among available hardware connections; the optimizer places interacting qubits at physical locations having high CNOT reliability; and GreedyE maps an interacting endpoint to the location maximizing total CNOT reliability with already placed qubits. It would therefore have been obvious, in applying Murali’s reliability-aware mapping to each of Akahoshi’s parallel ancilla-generation groups, to cause the required two-qubit rotation to operate on the available physical pair having the lowest applicable two-qubit-gate error, because that pair gives the greatest probability of successful execution and thus serves Murali’s expressly stated optimization objective.
Claim 7: Akahoshi and Murali teach the non-transitory computer-readable recording medium according to claim 1, wherein the process further includes instructing, upon determining that a time to execute the phase rotation gate has come during execution of a quantum circuit by the quantum computer, the quantum computer to execute the ancilla state generation circuit using the first plurality of qubit groups. For instance, Akahoshi, in Section V, explains that an ancilla state for the next RUS step can be prepared in an available logical patch while the present operation is being carried out, allowing subsequent rotation processing to begin with minimal overhead.
Claims 8 and 9 recite method/apparatus limitations that substantially correspond to the non-transitory computer-readable recording medium of claim 1. Accordingly, claims 8 and 9 are rejected under 35 U.S.C. § 103 for substantially the same reasons set forth above with respect to the non-transitory computer-readable recording medium claim.
Claim(s) 5 is rejected under 35 U.S.C. 103 as being unpatentable over Akahoshi and Murali as applied to claim 4 above, and further in view of Feizizadeh et al., “GIS-based ordered weighted averaging and Dempster–Shafer methods for landslide susceptibility mapping in the Urmia Lake Basin, Iran,” International Journal of Digital Earth (2013).
Claim 5: Akahoshi and Murali teach the non-transitory computer-readable recording medium according to claim 4, but fail to teach that the selecting of the arrangement candidate includes calculating the evaluation index value for the calculation-target arrangement candidate using a formula including a weighted sum that involves multiplying each of the minimum error rates sorted in ascending order, detected respectively in the plurality of qubit groups included in the calculation-target arrangement candidate, by a weight that is greater than a weight used for a subsequent minimum error rate in the ascending order. However, Feizizadeh et al. teach an ordered weighted averaging technique in which input criterion values are ranked in ascending order and an aggregate evaluation value is calculated as a weighted sum of the ranked values. Feizizadeh et al., §3.3, Eqs. (4)–(5). Equation (5) assigns the order weight
> v_k=\frac{n-r_k+1}{\sum_{j=1}^{n}(n-r_j+1)},
>
where r_k represents rank position. Thus, for values arranged in ascending order, an earlier-ranked value is assigned a greater order weight than a subsequently ranked value.
It would have been obvious to one of ordinary skill in the art to employ the known ordered-weighted aggregation technique of Feizizadeh when calculating Murali’s reliability-based evaluation of Akahoshi’s alternative qubit-group arrangements, because the technique provides a known way of aggregating a plurality of reliability/error criteria while intentionally giving greater influence to the more highly prioritized ranked values. Such a modification would have amounted to the use of a known data-aggregation technique for its established purpose of producing a single evaluation value from multiple ranked criteria.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Chang et al. “Innovative reliability allocation using the maximal entropy ordered weighted averaging method,” Computers & Industrial Engineering, vol. 57, no. 4, pp. 1274–1281 (2009).
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