DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/13/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-8, 11-12, 14-16, and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tominaga (US 2006/0140027 A1).
Regarding claim 1, Tominaga teaches a system for swapping faulty memory addresses in a microcontroller, the system comprising:
a fault detection circuitry to detect a faulty memory address in a first memory (defective addresses are detected and stored in non-volatile memory, ¶0004);
a blacklist register to store the faulty memory address detected by the fault detection circuitry (Fig. 4, Register Group 30 and Second Flash Memory 20 stores faulty memory address);
a comparator to compare a target memory address for a requested operation with the faulty memory address stored in the blacklist register (Fig. 4, Decoder 14 compares target address with faulty memory address stored in register 30); and
a control circuitry to, in response to a match between the target memory address and the faulty memory address stored in the blacklist register, direct the requested operation to a functional memory address in a second memory (Fig. 6, step S15).
Regarding claim 2, Tominaga further teaches the system of claim 1, further comprising a memory controller to access the first memory and the second memory (Fig. 2, Central Processing Unit (CPU) access the first and second memory ).
Regarding claim 3, Tominaga further teaches the system of claim 1, wherein the fault detection circuitry comprises a software diagnostic to detect the faulty memory address in the first memory (memory device software will detect if there is a problem with a storage area cell or sector and replace it with the redundant storage area, ¶0004).
Regarding claim 5, Tominaga further teaches the system of claim 1, wherein the blacklist register is volatile, and the faulty memory address is cleared in response to a reset of the microcontroller (Fig. 4, Register Group 30 is a volatile memory storage which requires data to be read from the non-volatile memory 21 and stored in the Register Group 30 when memory is powered on, ¶0045).
Regarding claim 6, Tominaga further teaches the system of claim 1, wherein the blacklist register is non-volatile, and the faulty memory address is persistently stored (Fig. 4, faulty memory addresses are stored in Second Flash Memory 21, which can be considered a non-volatile register. The data stored in the flash is maintained even when there is no power supply).
Regarding claim 7, Tominaga further teaches the system of claim 1, wherein the first memory comprises one of a volatile memory and a non-volatile memory (Fig. 4, memory 20 is a non-volatile memory).
Regarding claim 8, Tominaga further teaches the system of claim 1, wherein the second memory comprises a pre-defined set of memory addresses reserved for when the requested operation is directed to the second memory (Fig. 2, memory device 11 comprises a set of memory addresses reserved for redundant data storage area, which are used to replace defective addresses).
Regarding claims 11, 12, 14-16 and 18, the claims have similar limitations as claims 1-3 and 5-8 except they are written in a different format. Therefore, the claims are rejected under the same grounds of rejection.
Claim(s) 1, 10, 11, 18 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Moogat et al. (US 2007/0223292 A1).
Regarding claim 1, Moogat teaches a system for swapping faulty memory addresses in a microcontroller, the system comprising:
a fault detection circuitry to detect a faulty memory address in a first memory (defective addresses are detected and stored in non-volatile memory, ¶0006);
a blacklist register to store the faulty memory address detected by the fault detection circuitry (Fig. 1, Defect Map 216 stores faulty memory address);
a comparator to compare a target memory address for a requested operation with the faulty memory address stored in the blacklist register (Fig. 1, Compare Logic 220 compares target address with faulty memory address stored in register 216); and
a control circuitry to, in response to a match between the target memory address and the faulty memory address stored in the blacklist register, direct the requested operation to a functional memory address in a second memory (¶0044).
Regarding claim 10, Moogat further teaches the system of claim 1, wherein the comparator outputs a signal to a multiplexer to cause the multiplexer to output data received from one of the first memory and the second memory (Fig. 12, User column Decoder 450 and Redundant Column Decoder 450, are multiplexers which will output data from the first memory or redundant memory based on the result of the compare circuits signals Ay and Ay’).
Regarding claims 11, 18 and 20, the claims have similar limitations as claims 1 and 20 except the claims are written in a different format. Therefore, the claims are rejected under the same grounds of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 4 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tominaga as applied to claims 1 and 11 above, and further in view of Kim (US 2022/0208293 A1).
Regarding claims 4 and 13, Tominaga does not explicitly teach wherein the fault detection circuitry comprises an error correcting code (ECC) circuitry. However, ECC circuitry is inherent to correct and repair memory device. To expedite prosecution Kim is used to teach a memory device comprising an error correcting code (ECC) circuitry (Fig. 1, ECC circuit 400). Thus, it would have been obvious to a person with the ordinary skill in the art before the effective filing date of the claimed invention to use ECC circuitry to repair and correct errors in the memory device which can result in losing data if errors were not corrected and damage addresses were not repaired.
Claim(s) 9, 17 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tominaga as applied to claims 1, 11 and 18 above, and further in view of Moogat et al. (US 2007/0223292 A1).
Regarding claims 9, 17 and 19, Tominaga teaches when the target address and faulty memory address match, the compare signal will indicate to the memory device to read from the redundant location. Tominaga is silent in teaching the control circuity activates a bus stall signal during the memory operation, which is performed when addresses are matched.
Moogat teaches the control circuity activates a bus stall signal (Fig. 2A and Fig. 3A, the memory device will send a bus busy signal to the host when the memory device is performing the memory operation).
Thus, it would have been obvious to a person with the ordinary skill in the art before the effective filing date of the claimed invention to send a busy signal to the host in order to have a communication between the memory device and host that the memory is busy and can’t receive a new command until the first one is processed in order to prevent errors.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAMDAN N ALROBAIE whose telephone number is (571)270-7099. The examiner can normally be reached Monday to Thursday (8AM till 6PM).
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/Khamdan N. Alrobaie/Primary Examiner, Art Unit 2824
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